| _2025-03-28_10：29：49_ | 2025-03-28 10：29：49 | | Google AI芯片TPU核心架构--脉动阵列Systolic Array - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 AI | | Summary: Google's TPU (Tensor Processing Unit) is a specialized chip designed for artificial intelligence applications, with its core component being the "Matrix Multiply Unit." This unit uses a Systolic Array, a pulsing array, to enhance the speed and power efficiency of AI tasks, particularly in regards to convolution and matrix multiplication. The Systolic Array in TPU's architecture is the main focus, which is built around this matrix multiplication unit. It is accompanied by other data units like Unified Buffer and Weight FIFO, as well as activation pooling calculation units. | |
| _2024_7_10_16_35_44_ | 2024_7_10 16_35_44 | | AI时代进击的CPU们 | | 原文链接失效了?试试备份 | | TAGs:处理器 | | saved date: Wed Jul 10 2024 16:35:44 GMT+0800 (中国标准时间) | |
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| _2025-03-24_20：05：05_ | 2025-03-24 20：05：05 | | CXL Deep Dive – Future of Composable Server Architecture and Heterogeneous Compute, Products From 20 Firms, Overview of 3.0 St | | 原文链接失效了?试试备份 | | TAGs:处理器 CXL | | Summary: This text is about the Compute Express Link (CXL) standard, which aims to enable heterogeneous compute and composable server architectures by establishing an industry-standard protocol for connecting various chips together. CXL builds upon the existing PCIe 5.0 infrastructure but adds coherency and low-latency memory transactions. The article discusses the importance of CXL for the datacenter industry and its potential impact on memory pooling and switching. CXL 1.1 supports CXL.io, CXL.cache, and CXL.mem, and versions 2.0 and 3.0 bring additional features like memory sharing and device-to-device communications. Companies like Intel, AMD, Nvidia, and others are expected to release CXL products.本文是关于 Compute Express Link （CXL） 标准的，该标准旨在通过建立用于将各种芯片连接在一起的行业标准协议来实现异构计算和可组合服务器架构。CXL 建立在现有的 PCIe 5.0 基础设施之上，但增加了一致性和低延迟内存事务。本文讨论了 CXL 对数据中心行业的重要性及其对内存池和交换的潜在影响。CXL 1.1 支持 CXL.io、CXL.cache 和 CXL.mem，版本 2.0 和 3.0 带来了内存共享和设备到设备通信等附加功能。预计 Intel、AMD、Nvidia 等公司将发布 CXL 产品。 | |
| _2025-03-24_20：03：40_ | 2025-03-24 20：03：40 | | CXL 深度解析：可组合服务器与异构计算的未来 - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 CXL | | Summary: This article discusses the future of composable server architecture and heterogeneous compute using the CXL (Compute Express Link) interface. CXL is a standard for high-speed serial communication between processors and memory devices. The article covers the evolution of CXL from version 1 to 3 and the products and strategies of 20 companies in the field, including Intel, AMD, Nvidia, and others. The article emphasizes the importance of understanding the impact of CXL on data centers and the opportunities and challenges it presents for the semiconductor industry. The article also discusses the benefits of CXL for memory sharing and reducing DRAM requirements. The focus is on non-packaged features, with packaging features to be discussed in a separate article on UCIe. The article was originally published by WF Research, a professional research firm specializing in first principles.本文讨论了使用 CXL （Compute Express Link） 接口的可组合服务器架构和异构计算的未来。CXL 是处理器和内存设备之间高速串行通信的标准。本文涵盖了 CXL 从版本 1 到 3 的演变，以及该领域 20 家公司的产品和战略，包括 Intel、AMD、Nvidia 等。本文强调了了解 CXL 对数据中心的影响及其为半导体行业带来的机遇和挑战的重要性。本文还讨论了 CXL 在内存共享和降低 DRAM 需求方面的优势。重点是非打包功能，打包功能将在 UCIe 上的单独文章中讨论。本文最初由 WF Research 发表，这是一家专门研究第一性原理的专业研究公司。 | |
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| _2024_8_4_17_39_40_ | 2024_8_4 17_39_40 | | - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 GPU | | saved date: Sun Aug 04 2024 17:39:40 GMT+0800 (中国标准时间) | |
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| _2024_8_2_10_54_19_ | 2024_8_2 10_54_19 | | OpenGPGPU | | 原文链接失效了?试试备份 | | TAGs:处理器 GPU | | saved date: Fri Aug 02 2024 10:54:19 GMT+0800 (中国标准时间) | |
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| _2024_8_2_17_32_38_ | 2024_8_2 17_32_38 | | | 原文链接失效了?试试备份 | | TAGs:处理器 GPU 内存 | | saved date: Fri Aug 02 2024 17:32:38 GMT+0800 (中国标准时间) | |
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| _2024_8_1_16_14_15_ | 2024_8_1 16_14_15 | | 围剿英伟达 | | 原文链接失效了?试试备份 | | TAGs:处理器 GPU | | saved date: Thu Aug 01 2024 16:14:15 GMT+0800 (中国标准时间) | |
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| _2024_8_26_10_15_03_ | 2024_8_26 10_15_03 | | 一文读懂高通GPU驱动渲染流程 | | 原文链接失效了?试试备份 | | TAGs:处理器 GPU 驱动 | | saved date: Mon Aug 26 2024 10:15:03 GMT+0800 (中国标准时间) | |
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| _数字芯片的面积优化：第三届“华为杯”研究生创芯大赛数字方向上机题1详解_wire_load_ | 数字芯片的面积优化：第三届“华为杯”研究生创芯大赛数字方向上机题1详解_wire load | | has zero net area-CSDN博客 PPA | | 原文链接失效了?试试备份 | | TAGs:处理器 PPA | | saved date: Thu Dec 26 2024 20:17:16 GMT+0800 (中国标准时间) | |
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| _2024_8_29_12_42_41_ | 2024_8_29 12_42_41 | | Arm中国的人、命、运 | | 原文链接失效了?试试备份 | | TAGs:处理器 arm | | saved date: Thu Aug 29 2024 12:42:41 GMT+0800 (中国标准时间) | |
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| _2024_10_29_14_47_52_ | 2024_10_29 14_47_52 | | 芯片启动 - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 boot | | saved date: Tue Oct 29 2024 14:47:52 GMT+0800 (中国标准时间) | |
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| _2025-06-05_14：43：03_ | 2025-06-05 14：43：03 | | High RISC, High Reward_ RISC-V at 15 – RISC-V International | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | Summary: RISC-V is an open-source instruction set architecture (ISA) that was developed at the University of California, Berkeley, starting in 2010. The team, led by Krste Asanović and Andrew Waterman, aimed to create a clean slate for compute architecture, free from the limitations of existing ISAs. They wanted to build a flexible, extensible, and easily customizable ISA that could meet the demands of specialized, customizable, and parallel computing. | |
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| _2025-04-29_11：59：18_ | 2025-04-29 11：59：18 | | iommu_riscv_ fix use after free of riscv_iommu_domain - Patchwork | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v IOMMU | | Summary: This text is an email message about a patch for the RISC-V IOMMU driver in the Linux kernel. The patch addresses a use-after-free issue in the `riscv_iommu_bond_unlink` function. The issue occurs when the `riscv_iommu_domain` is freed but not set to NULL before being used in `riscv_iommu_attach_paging_domain` and `riscv_iommu_bond_unlink`. The patch sets `info->domain` to NULL within `riscv_iommu_bond_unlink` to resolve the issue. The email includes the patch diff and a commit message.此文本是有关 Linux 内核中 RISC-V IOMMU 驱动程序补丁的电子邮件。此补丁解决了“riscv_iommu_bond_unlink”函数中的释放后使用问题。当“riscv_iommu_domain”在“riscv_iommu_attach_paging_domain”和“riscv_iommu_bond_unlink”中使用之前被释放但未设置为 NULL 时，会出现此问题。该补丁将“riscv_iommu_bond_unlink”中的“info->domain”设置为 NULL 以解决此问题。该电子邮件包括 patch diff 和提交消息。 | |
| _2025-03-18_20：13：33_ | 2025-03-18 20：13：33 | | [4_4] iommu_riscv_ Add support for Svnapot - Patchwork | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v IOMMU svnapot | | Summary: This text is an email message containing a patch for the RISC-V IOMMU driver in the Linux kernel. The patch adds support for the Svnapot page size in the IOMMU driver. The email includes various headers and signatures indicating the source and history of the patch. The patch itself consists of adding new functions and modifying existing ones in the iommu.c file to handle Svnapot page sizes. The patch also includes comments and tests to ensure the correct functionality.此文本是一封电子邮件，其中包含 Linux 内核中 RISC-V IOMMU 驱动程序的补丁。此修补程序在 IOMMU 驱动程序中添加了对 Svnapot 页面大小的支持。该电子邮件包含各种标头和签名，用于指示补丁的来源和历史记录。补丁本身包括添加新函数和修改 iommu.c 文件中的现有函数，以处理 Svnapot 页面大小。该补丁还包括注释和测试，以确保功能正确。 | |
| _2025-03-27_17：49：34_ | 2025-03-27 17：49：34 | | [RESEND,v2,4_4] iommu_riscv_ Add support for Svnapot - Patchwork | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v IOMMU svnapot | | Summary: This text is an email message containing a patch series for the RISC-V IOMMU driver in the Linux kernel. The patch series aims to add support for Svnapot, a specific page size, in the IOMMU driver. The patch series includes five individual patches, each addressing a specific aspect of the implementation. The first patch adds the Svnapot size as a supported page size and applies it when possible. The remaining patches handle the allocation and freeing of Svnapot-sized pages in the IOMMU driver. The email also includes various headers and metadata, such as the sender, recipients, subject, and date.此文本是一封电子邮件，其中包含 Linux 内核中 RISC-V IOMMU 驱动程序的补丁系列。该补丁系列旨在在 IOMMU 驱动程序中添加对 Svnapot（一种特定页面大小）的支持。补丁系列包括五个单独的补丁，每个补丁都涉及实施的特定方面。第一个补丁将 Svnapot 大小添加为支持的页面大小，并在可能的情况下应用它。其余补丁处理 IOMMU 驱动程序中 Svnapot 大小的页面的分配和释放。该电子邮件还包括各种标头和元数据，例如发件人、收件人、主题和日期。 | |
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| _2025-06-13_15：48：51_ | 2025-06-13 15：48：51 | | 解析RISCV fence指令 - RISC-V - 进迭RISC-V论坛 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA FENCE | | Summary: This text discusses the use of fence instructions in the RISC-V instruction set to ensure ordered memory access for specific software scenarios. Fence instructions ensure that operations before the fence occur before those after it, preventing unpredictable results. The text provides an example of how fence instructions are used to ensure the order of store and load operations for two cores. It also explains the different formats and uses of fence instructions, including fence.i for ensuring ordered memory access for instruction fetch.本文讨论了在 RISC-V 指令集中使用 fence 指令来确保特定软件场景的有序内存访问。围栏指令可确保围栏之前的作先于围栏之后的作发生，从而防止出现不可预知的结果。该文本提供了一个示例，说明如何使用 fence 指令来确保两个内核的 store 和 load 作的顺序。它还解释了 fence 指令的不同格式和用法，包括 fence.i 以确保指令获取的有序内存访问。 | |
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| _2025-02-28_14：00：26_ | 2025-02-28 14：00：26 | | tech-attached-matrix-extension@lists.riscv.org _RISC-V AME 扩展的 SiFive 提案 --- tech-attached-matrix-extension@lists.riscv.org _ | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA Matrix | | Summary: This text is a discussion between team members regarding the Zvma Attached Matrix Extension (AME) proposal. They find the specification clear and elegant, offering significant matrix computation bandwidth while maintaining software-friendliness. However, they have some concerns about physical design friendliness, specifically the placement of matrix computation logic alongside RAM/flop states and the potential routing contention between the computation block and on-chip memory. They suggest making the data layout microarchitecture (uarch) defined instead of locked at the ISA level and allowing alternative punning schemes in future extensions for greater flexibility. They also recommend specifying that matrix data should be marked as "unspecified" following any matrix configuration change. The team is considering the uarch based on the proposal and looks forward to continued collaboration as Zvma progresses toward ratification.本文是团队成员之间关于 Zvma 附加矩阵扩展 （AME） 提案的讨论。他们发现规范清晰而优雅，在保持软件友好性的同时提供了大量的矩阵计算带宽。然而，他们对物理设计友好性有一些担忧，特别是矩阵计算逻辑与 RAM/flop 状态一起放置，以及计算块和片上存储器之间潜在的路由争用。他们建议在 ISA 级别定义而不是锁定数据布局微架构 （uarch），并在未来的扩展中允许使用其他双关模式以获得更大的灵活性。他们还建议指定在矩阵配置更改后应将矩阵数据标记为“未指定”。该团队正在根据该提案考虑 uarch，并期待在 Zvma 获得批准的过程中继续合作。 | |
| _2025-02-28_14：05：35_ | 2025-02-28 14：05：35 | | tech-attached-matrix-extension@lists.riscv.org _RISC-V AME 扩展的 SiFive 提案 --- tech-attached-matrix-extension@lists.riscv.org _ | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA Matrix | | Summary: The text discusses a feedback exchange between team members regarding the Zvma Attached Matrix Extension (AME) proposal. The team, T1, has reviewed the proposal and finds it clear and elegant, offering significant matrix computation bandwidth while maintaining software-friendliness. They suggest some improvements, including making the data layout microarchitecture (uarch) defined instead of locked at the ISA level, addressing consistency challenges in multi-core scenarios, and specifying that matrix data should be marked as "unspecified" following any matrix configuration change. They also discuss concerns about physical design friendliness, specifically the placement of matrix computation logic alongside RAM/flop states and the potential routing contention between the computation block and on-chip memory. They emphasize the importance of addressing these issues to ensure high-performance computation and alignment across different uarch designs.本文讨论了团队成员之间关于 Zvma 附加矩阵扩展 （AME） 提案的反馈交流。T1 团队审查了该提案，发现它清晰而优雅，在保持软件友好性的同时提供了大量的矩阵计算带宽。他们提出了一些改进建议，包括在 ISA 级别定义而不是锁定数据布局微架构 （uarch），解决多核场景中的一致性挑战，以及指定在任何矩阵配置更改后应将矩阵数据标记为 “unspecified”。他们还讨论了对物理设计友好性的担忧，特别是矩阵计算逻辑与 RAM/flop 状态一起放置，以及计算块和片上存储器之间潜在的布线争用。他们强调了解决这些问题的重要性，以确保不同 uarch 设计之间的高性能计算和对齐。 | |
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| _2025-04-11_11：28：55_ | 2025-04-11 11：28：55 | | RISC-V 密码学指令扩展（K扩展）功能概述 - WuSiYu Blog | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: This blog post is about RISC-V's cryptographic extension (K extension) for IT-related experiments. The K extension provides a series of cryptography-related instructions, which are similar to other instructions in terms of using general registers and maintaining the principle of two reads and one write. Compared to software implementation, using these instructions can enhance the speed of cryptographic algorithms and reduce the size of applications. | |
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| _2025-04-18_19：26：06_ | 2025-04-18 19：26：06 | | The RISC-V Instruction Set Manual_ Volume II_ Privileged Architecture | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: This document describes the RISC-V privileged architecture, which covers aspects of RISC-V systems beyond the unprivileged ISA. It includes privileged instructions and additional functionality required for running operating systems and attaching external devices. The document includes the terminology used for different software stack components, the concept of privilege levels, and the use of control and status registers (CSRs). The RISC-V architecture supports three privilege levels: Machine, Supervisor, and User. The Machine level has the highest privileges and is the only mandatory privilege level for a RISC-V hardware platform. The Supervisor level is used for operating systems and other privileged software, while the User level is used for applications. The document also discusses debug mode and control and status registers (CSRs), including their address mapping conventions and a CSR listing. The CSR address space is divided into unprivileged and user-level CSRs, supervisor-level CSRs, hypervisor and virtual supervisor CSRs, and machine-level CSRs. The document also mentions the Zicsr extension, which is required for all RISC-V implementations, and the SYSTEM major opcode used for all privileged instructions.本文档介绍了 RISC-V 特权体系结构，它涵盖了非特权 ISA 之外的 RISC-V 系统的各个方面。它包括运行作系统和连接外部设备所需的特权指令和附加功能。本文档包括用于不同软件堆栈组件的术语、权限级别的概念以及控制和状态寄存器 （CSR） 的使用。RISC-V 架构支持三个权限级别：Machine、Supervisor 和 User。Machine 级别具有最高权限，并且是 RISC-V 硬件平台的唯一强制权限级别。Supervisor 级别用于作系统和其他特权软件，而 User 级别用于应用程序。本文档还讨论了调试模式以及控制和状态寄存器 （CSR），包括它们的地址映射约定和 CSR 列表。CSR 地址空间分为非特权和用户级 CSR、主管级 CSR、虚拟机管理程序和虚拟主管 CSR 以及计算机级 CSR。该文档还提到了 Zicsr 扩展，这是所有 RISC-V 实现所必需的，以及用于所有特权指令的 SYSTEM 主要作码。 | |
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| _2025-05-23_16：12：49_ | 2025-05-23 16：12：49 | | 进迭时空RISC-V Vector技术实践 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA Vector | | Summary: This text discusses the benefits of RISC-V Vector, a more flexible programming model compared to traditional SIMD instructions, in improving the decoupling between software and hardware. RISC-V Vector supports single instruction multiple data parallel processing while providing higher-level abstractions for developers. The text uses RISC-V Vector 1.0 as an example, explaining how it allows a single program to run on hardware with different vector register widths, and how the element mask function handles excess elements without requiring special handling like in SIMD instructions. The text also mentions that the first-generation RISC-V CPUs, X60 and A60, support RISC-V Vector 1.0 and provide significant performance improvements in various tests compared to Cortex-A55's SIMD instructions.本文讨论了 RISC-V Vector（与传统 SIMD 指令相比，RISC-V Vector）是一种更灵活的编程模型，在改善软件和硬件之间的解耦方面的优势。RISC-V Vector 支持单指令多数据并行处理，同时为开发人员提供更高级别的抽象。本文以 RISC-V Vector 1.0 为例，解释了它如何允许单个程序在具有不同矢量寄存器宽度的硬件上运行，以及元素掩码函数如何处理多余的元素，而无需像 SIMD 指令那样进行特殊处理。文中还提到，第一代 RISC-V CPU X60 和 A60 支持 RISC-V Vector 1.0，与 Cortex-A55 的 SIMD 指令相比，在各种测试中提供了显著的性能改进。 | |
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| _2025-03-25_14：43：07_ | 2025-03-25 14：43：07 | | riscv-profiles_src_rvb23-profile.adoc at main · riscv_riscv-profiles | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: The provided text is a GitHub page about the RVB23 profile for RISC-V application processors. It outlines the mandatory and optional ISA features available to user-mode (RVB23U64) and supervisor-mode (RVB23S64) execution environments in 64-bit RVB applications processors. The page also mentions various extensions and options, some of which are localized, development, expansion, or transitory. The RVB23 profile is a customizable 64-bit application processor profile that provides a large set of features but allows optionality for more expensive and targeted extensions.提供的文本是有关 RISC-V 应用程序处理器的 RVB23 配置文件的 GitHub 页面。它概述了 64 位 RVB 应用处理器中的用户模式 （RVB23U64） 和监控器 模式 （RVB23S64） 执行环境可用的强制性和可选 ISA 功能。该页面还提到了各种扩展和选项，其中一些是本地化的、开发的、扩展的或临时的。RVB23 配置文件是一种可定制的 64 位应用处理器配置文件，它提供大量功能，但允许选择更昂贵和有针对性的扩展。 | |
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| _2025-02-26_11：29：14_ | 2025-02-26 11：29：14 | | tech-announce@lists.riscv.org _ Public review for Smctr_Ssctr ISA extensions | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: The RISC-V Foundation has initiated a public review period for the proposed Control Transfer Records (Smctr/Ssctr) standard extensions to the RISC-V Instruction Set Architecture (ISA). The review period, which runs from July 23 to August 22, 2024, invites feedback via email or GitHub. The extensions, described in the PDF specification available at github.com, aim to correct and incorporate minor changes during the review process. The Privileged ISA Committee will recommend approval and ratification upon completion of the review. (by Mozilla Orbit AI) | |
| _2025-03-24_10：26：06_ | 2025-03-24 10：26：06 | | wfi __ RISC-V Specification for generic_rv64 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: This page describes the behavior of the wfi (Wait For Interrupt) instruction in the RV64 generic architecture. The instruction causes the processor to enter a low-power state and wait for an interrupt. The behavior of wfi is influenced by the mstatus and hstatus registers. In certain modes and conditions, wfi may cause a trap leading to an Illegal Instruction or Virtual Instruction exception.本页介绍 RV64 通用体系结构中 wfi （等待中断） 指令的行为。该指令使处理器进入低功耗状态并等待中断。wfi 的行为受 mstatus 和 hstatus 寄存器的影响。在某些模式和条件下，wfi 可能会导致导致非法指令或虚拟指令异常的陷阱。 | |
| _2025-03-25_10：58：25_ | 2025-03-25 10：58：25 | | [1_5] RISC-V_ KVM_ Forward SEED CSR access to user space - Patchwork | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA zkr | | Summary: This text appears to be an email message containing a patch series for the RISC-V KVM (Kernel-based Virtual Machine) project. The patch series is related to forwarding SEED CSR (Control and Status Register) access to user space when the Zkr extension is available to the guest/VM. The patch includes changes to the `arch/riscv/kvm/vcpu_insn.c` file and is signed off by Anup Patel and reviewed by Andrew Jones. The patch series also includes metadata such as the list ID, mailman version, and sender information.此文本似乎是一封电子邮件，其中包含 RISC-V KVM（基于内核的虚拟机）项目的补丁系列。此补丁系列与当 Zkr 扩展可供来宾/VM 使用时将 SEED CSR（控制和状态寄存器）访问转发到用户空间有关。此补丁包括对 'arch/riscv/kvm/vcpu_insn.c' 文件的更改，由 Anup Patel 签署并由 Andrew Jones 审阅。修补程序系列还包括元数据，例如列表 ID、mailman 版本和发件人信息。 | |
| _2025-03-25_10：58：17_ | 2025-03-25 10：58：17 | | [PULL,02_28] target_riscv_kvm_ Fix exposure of Zkr - Patchwork | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA zkr | | Summary: This text is a diff output showing changes made to the RISC-V QEMU emulator code. The changes include adding a new function `riscv_new_csr_seed()` to create a new value for the SEED CSR, and updating the `rmw_seed()` function to use this new function instead of generating a random value directly. The changes also include adding a new case `KVM_EXIT_RISCV_CSR` to the `kvm_arch_handle_exit()` function to handle the CSR EXIT reason.此文本是一个差异输出，显示了对 RISC-V QEMU 仿真器代码所做的更改。这些更改包括添加新函数 'riscv_new_csr_seed（）' 为 SEED CSR 创建新值，以及更新 'rmw_seed（）' 函数以使用此新函数，而不是直接生成随机值。这些更改还包括向 'kvm_arch_handle_exit（）' 函数添加新的 case 'KVM_EXIT_RISCV_CSR' 来处理 CSR EXIT 原因。 | |
| _2025-04-10_15：22：41_ | 2025-04-10 15：22：41 | | tech-privileged@lists.riscv.org _ [RISC-V] [tech-crypto-ext] Read the seed CSR | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA zkr | | Summary: This discussion revolves around the behavior of the seed CSR (Control and Status Register) in a cryptographic system. The seed CSR is designed to ensure that secret entropy words are not made available multiple times for security reasons. When reading the seed CSR, the system clears (wipes) the entropy contents and changes the state to WAIT, unless there is entropy immediately available for ES16. However, there is a discrepancy between the seed CSR specification and the privileged specification regarding the side effects of reads and writes. | |
| _2025-02-28_13：35：26_ | 2025-02-28 13：35：26 | | 从向量到矩阵：RISC-V 矩阵扩展的未来 - 知乎 --- From Vector to Matrix_ The Future of RISC-V Matrix Extensions - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: This text is about the development and future possibilities of Matrix Extensions in RISC-V, a open-source Instruction Set Architecture (ISA). The text discusses various matrix extension proposals, such as Integrated Matrix Extension from Spacemit and Attached Matrix Extension from Xuantie, Stream Computing, and SiFive (Zvma). The author compares the tradeoffs between Integrated and Attached Matrix Extensions, and the relationship between existing Vector Extensions and Matrix Extensions. The text also explores potential hardware implementations of RISC-V matrix acceleration.本文介绍了 RISC-V（一种开源指令集架构 （ISA））中矩阵扩展的开发和未来可能性。本文讨论了各种矩阵扩展提案，例如 Spacemit 的 Integrated Matrix Extension 和 Xuantie 的 Attached Matrix Extension、Stream Computing 和 SiFive （Zvma）。作者比较了 Integrated Matrix Extensions 和 Attached Matrix Extensions 之间的权衡，以及现有 Vector Extensions 和 Matrix Extensions 之间的关系。本文还探讨了 RISC-V 矩阵加速的潜在硬件实现。 | |
| _2025-02-28_13：40：48_ | 2025-02-28 13：40：48 | | 玄铁矩阵乘法扩展说明 – RISC-V International --- XuanTie Matrix Multiply Extension Instructions – RISC-V International | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: The text discusses the XuanTie Matrix Multiply Extension (MME) for RISC-V processors, designed to meet the demands for AI computing power with independent matrix extensions. The benefits of independent matrix extensions include independent programming models, developer-friendly design, and simplified hardware implementation. The XuanTie MME includes matrix multiply-accumulate instructions, matrix load/store instructions, and other matrix computations to improve AI computing power. The extension supports various data types and sizes and is scalable, portable, and decoupled from vector extensions. The design has been open-sourced on GitHub for further development.本文讨论了用于 RISC-V 处理器的 XuanTie 矩阵乘法扩展 （MME），旨在通过独立的矩阵扩展满足对 AI 计算能力的需求。独立矩阵扩展的优势包括独立的编程模型、开发人员友好的设计和简化的硬件实现。炫铁 MME 包括矩阵乘法累加指令、矩阵加载/存储指令和其他矩阵计算，以提高 AI 计算能力。该扩展支持各种数据类型和大小，并且可扩展、可移植，并且与矢量扩展分离。该设计已在 GitHub 上开源，以供进一步开发。 | |
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| _2024_10_15_09_51_25_ | 2024_10_15 09_51_25 | | RAS 调研 _ blog | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v RAS | | saved date: Tue Oct 15 2024 09:51:25 GMT+0800 (中国标准时间) | |
| _2024_10_15_22_32_33_ | 2024_10_15 22_32_33 | | RAS 调研 _ blog | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v RAS | | saved date: Tue Oct 15 2024 22:32:33 GMT+0800 (中国标准时间) | |
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| _2025-02-26_16：35：36_ | 2025-02-26 16：35：36 | | RISC-V Non-ISA Specifications | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | Summary: This text describes the RISC-V Non-ISA Specifications repository on GitHub, which contains non-instruction set architecture specifications for RISC-V. These specifications include documentation, architecture tests, and specifications for various interfaces and tools. The repository includes several sub-repositories, each focusing on different aspects of the RISC-V ecosystem. The text also mentions that the repository does not modify the RISC-V Instruction Set Architecture and provides a list of popular repositories. | |
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| _2025-03-10_16：47：33_ | 2025-03-10 16：47：33 | | RISC-V 软件：2024 年重大进展与 2025 年展望 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v RISC-V Software Ecosystem | | Summary: SiFive Inc., a leading RISC-V chip manufacturer based in Taiwan, has seen significant progress in RISC-V software development in 2024. Key achievements include the enhancement of language runtime environments, the release of RISC-V optimization guidelines, and the support of RISC-V vector instructions in Linux kernels. In 2025, SiFive will focus on optimizing software for the recently introduced RVA23 Profile hardware. Additionally, SiFive is working on delivering optimized code for their processors, particularly in the field of artificial intelligence. The company has shown a reference software stack for running large language models on their RISC-V intelligent products and discussed internal test results at a webinar. SiFive is also collaborating with upstream data center companies to optimize and port various software stacks for RISC-V. While significant progress has been made in RISC-V software development, there is still work to be done, and SiFive plans to continue optimizing software and collaborating with RISE and other ecosystem partners to accelerate the growth of the RISC-V ecosystem.SiFive Inc. 是一家总部位于台湾的领先 RISC-V 芯片制造商，在 2024 年见证了 RISC-V 软件开发的重大进展。主要成就包括增强语言运行时环境、发布 RISC-V 优化指南以及在 Linux 内核中支持 RISC-V 矢量指令。2025 年，SiFive 将专注于优化最近推出的 RVA23 Profile 硬件的软件。此外，SiFive 正在努力为其处理器提供优化的代码，尤其是在人工智能领域。该公司展示了在其 RISC-V 智能产品上运行大型语言模型的参考软件堆栈，并在网络研讨会上讨论了内部测试结果。SiFive 还与上游数据中心公司合作，为 RISC-V 优化和移植各种软件堆栈。虽然 RISC-V 软件开发取得了重大进展，但仍有工作要做，SiFive 计划继续优化软件并与 RISE 和其他生态系统合作伙伴合作，以加速 RISC-V 生态系统的发展。 | |
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| _2025-03-10_16：50：53_ | 2025-03-10 16：50：53 | | riscv-profiles_src_rva23-profile.adoc at main · riscv_riscv-profiles | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v RISC-V Software Ecosystem riscv-profiles | | Summary: The RVA23 profiles are a set of specifications for RISC-V 64-bit application processors, with two profiles: RVA23U64 for user-mode and RVA23S64 for supervisor-mode. The RVA23 profiles aim to align implementations and enable binary software ecosystems to rely on a large set of guaranteed extensions and a small number of discoverable coarse-grain options. The profiles specify various mandatory and optional ISA features, including integer multiplication and division, atomic instructions, single- and double-precision floating-point instructions, vector extension, and more. The profiles also include extensions like instruction-fetch fence, control and status register access, and hardware performance counters.RVA23 配置文件是一组用于 RISC-V 64 位应用处理器的规范，包含两个配置文件：RVA23U64 用于用户模式，RVA23S64 用于管理器模式。RVA23 配置文件旨在调整实施，并使二进制软件生态系统能够依赖大量有保证的扩展和少量可发现的粗粒度选项。这些配置文件指定了各种强制性和可选的 ISA 功能，包括整数乘法和除法、原子指令、单精度和双精度浮点指令、向量扩展等。这些配置文件还包括 instruction-fetch fence、控制和状态寄存器访问以及硬件性能计数器等扩展。 | |
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| _2025-05-07_14：01：58_ | 2025-05-07 14：01：58 | | RVA23 Profile_ Unlocking new possibilities for RISC-V in high-performance, compute-intensive workloads | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | Summary: The RVA23 Profile is a new standard for 64-bit RISC-V application processors, recently ratified by RISC-V International. It ensures software portability and compatibility across hardware implementations, making it ideal for compute-intensive applications, particularly in AI, machine learning, and enterprise-level tasks. The RVA23 Profile includes mandatory Vector and Hypervisor extensions, which enable efficient data processing and virtualization support, respectively. This standardization positions RISC-V as a viable choice for high-performance servers and other compute-heavy systems.RVA23 Profile 是 64 位 RISC-V 应用处理器的新标准，最近获得了 RISC-V International 的批准。它确保了软件的可移植性和跨硬件实施的兼容性，使其成为计算密集型应用程序的理想选择，尤其是在 AI、机器学习和企业级任务中。RVA23 配置文件包括强制性的矢量和虚拟机管理程序扩展，分别支持高效的数据处理和虚拟化支持。这种标准化使 RISC-V 成为高性能服务器和其他计算密集型系统的可行选择。 | |
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| _2025_1_23_19：57：35_ | 2025_1_23 19：57：35 | | _sbi源代码分析-CSDN博客 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v SBI | | saved date: Thu Jan 23 2025 19:57:35 GMT+0800 (中国标准时间) | |
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| _2025-06-26_14：44：25_ | 2025-06-26 14：44：25 | | RISC-V Technical Specifications - Home - RISC-V Tech Hub | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v SPEC | | Summary: The RISC-V Technical Specifications page provides a comprehensive list of all ratified technical publications for the RISC-V instruction set architecture. This includes ISA specifications, profiles, and non-ISA specifications. The ISA specifications include the Unprivileged ISA and Privileged Architecture manuals. Profiles include the RVA23 and RISC-V Profiles 1.0. Non-ISA specifications cover various topics such as efficient trace for RISC-V, RISC-V ABIs, RISC-V Advanced Interrupt Architecture, and RISC-V Capacity and Bandwidth QoS Register Interface. The RISC-V Architectural Compatibility Test Framework is also available for ensuring model compatibility.RISC-V 技术规格页面提供了 RISC-V 指令集架构的所有已批准技术出版物的完整列表。这包括 ISA 规范、配置文件和非 ISA 规范。ISA 规范包括 Unprivileged ISA 和 Privileged Architecture 手册。配置文件包括 RVA23 和 RISC-V 配置文件 1.0。非 ISA 规范涵盖各种主题，例如 RISC-V 的高效跟踪、RISC-V ABI、RISC-V 高级中断架构以及 RISC-V 容量和带宽 QoS 寄存器接口。RISC-V 架构兼容性测试框架也可用于确保模型兼容性。 | |
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| _2025-03-02_11：24：49_ | 2025-03-02 11：24：49 | | riscv-non-isa_riscv-server-platform_ The RISC-V Server Platform specification defines a standardized set of hardware and sofwa | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v server | | Summary: The RISC-V Server Platform is a specification that outlines standardized hardware and software capabilities for portable system software, such as operating systems and hypervisors, in RISC-V servers. The document includes information about the specification, its history, and dependencies. Users can clone the project, build the PDF using the Makefile, and view the document's topics, which include platform, server, os, standards, interoperability, UEFi, hypervisors, ACPI, risc-v, and BRS-I. The project is licensed under a Creative Commons Attribution 4.0 International License and has 11 stars, 5 forks, and 8 watchers.RISC-V 服务器平台是一项规范，概述了 RISC-V 服务器中便携式系统软件（如作系统和虚拟机管理程序）的标准化硬件和软件功能。该文档包含有关规范、其历史记录和依赖项的信息。用户可以克隆项目，使用 Makefile 构建 PDF，并查看文档的主题，包括平台、服务器、作系统、标准、互作性、UEFi、虚拟机管理程序、ACPI、risc-v 和 BRS-I。该项目根据 Creative Commons Attribution 4.0 International License 获得许可，并拥有 11 颗星、5 个分叉和 8 个观察者。 | |
| _server_risc-v_ | server risc-v | | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v server | | saved date: Fri Feb 21 2025 19:17:42 GMT+0800 (中国标准时间) | |
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| _2025-06-26_16：22：19_ | 2025-06-26 16：22：19 | | soc-infra@lists.riscv.org _ Home | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | Summary: The SOC Infrastructure Horizontal committee is responsible for components straddling the hardware/software boundary in various products, from IoT to data centers. These components, which include those necessary for system boot and operation, often overlap with other committees such as security and RAS. The goal is to establish a comprehensive set of specifications for product implementers, reducing duplication and fragmentation within the RISC-V community.SOC 基础设施横向委员会负责从 IoT 到数据中心的各种产品中跨越硬件/软件边界的组件。这些组件（包括系统启动和作所需的组件）通常与其他委员会（如安全和 RAS）重叠。目标是为产品实施者建立一套全面的规范，减少 RISC-V 社区内的重复和碎片化。 | |
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| _2025-03-30_14：11：55_ | 2025-03-30 14：11：55 | | RISC-V SSTC扩展对Linux CRNG影响分析 - DeepSeek - 探索未至之境 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v timer SSTC random | | Summary: The user is asking for an analysis of the impact of RISC-V's SSTC extension on Linux's CRNG (Cryptographic Random Number Generator) and the getrandom system call. The SSTC extension may refer to "Supervisor Software Time Compare" or some time-related extension, but it's not clear without checking the search results. However, the user's question seems to involve RISC-V's security vulnerabilities or random number generation mechanisms. For instance, one page mentions that RISC-V enabled the general CPU vulnerability reporting feature in Linux 6.12 kernel, including the detection and mitigation status. This might be related to system security, which in turn affects the reliability of the random number generator. CRNG is a random number generation module in the Linux kernel, while getrandom is a system call for obtaining random numbers in user space. If RISC-V's SSTC extension introduces new instructions or hardware features, it may affect the efficiency or security of random number generation. For example, one page discusses RISC-V Linux entry address memory optimization, which might involve kernel startup time memory management but is not directly related to random number generation. Another page mentions RISC-V processor vulnerabilities, such as GhostWrite, which can impact system security and, consequently, CRNG's data source. If SSTC extension improves time stamping or counters, it may provide higher-quality interrupt sources or entropy sources for CRNG, thereby improving random number generation speed and quality. One page discusses RISC-V's development in the software ecosystem, including toolchain and compiler optimization, which may indirectly affect the implementation of random number generation in the kernel. For instance, new extensions may require kernel module adaptation and optimization of the entropy collection process. Additionally, pages 7 and 8 discuss RISC-V's integration with the open-source community, which might involve kernel developers supporting RISC-V's new features. If SSTC extension requires kernel-level modifications, such as in driver or architecture-related code, this may impact CRNG's implementation. In summary, while the search results do not directly mention SSTC extension, it can be inferred that SSTC may be a security or time-related extension, and its impact may include improving entropy source collection efficiency, enhancing random number generation security, or requiring kernel adaptation. For example, if SSTC provides hardware random number generation instructions, the kernel's CRNG may utilize these instructions to improve performance and reduce reliance on software entropy sources. Furthermore, vulnerability patches, such as the one mentioned in page 2, can strengthen CRNG's security by addressing hardware vulnerabilities that could lead to random number prediction risks. RISC-V's SSTC (Supervisor Software Time Compare) extension is a part of RISC-V's privileged architecture, primarily used for optimizing time management and interrupt handling. Its impact on Linux's CRNG and getrandom can be summarized as follows: | |
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| _2025-05-22_19：48：10_ | 2025-05-22 19：48：10 | | 万字长文：官方解读RISC-V | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | Summary: This text summarizes the story of the RISC-V processor architecture and its development over the past 15 years. The article begins with an email sent by a student, Andrew Waterman, to his professors in 2010, expressing his belief that they should revive the DEC Alpha microprocessor architecture. However, his professors, including Krste Asanović, saw the need for a new ISA due to the limitations of existing ISAs and the demands of Moore's Law and Dennard scaling. | |
| _2025-04-20_15：09：58_ | 2025-04-20 15：09：58 | | 6.S081——补充材料——RISC-V架构中的异常与中断详解_risc-v 中断设计-CSDN博客 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 中断 | | Summary: This blog post discusses the concept of exceptions and interrupts in the RISC-V architecture. It explains that exceptions are defined as unexpected situations that occur during instruction execution, while interrupts are caused by external asynchronous events. The post also covers the role of the Supervisor and Machine modes in handling exceptions and the use of the CSR registers in the exception handling process. The article also touches upon the concept of interrupt delegation and the difference between direct and vectorized exception handling. The post is intended for readers who are interested in the RISC-V architecture and its exception and interrupt handling mechanisms. | |
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| _2025_1_9_16：25：41_ | 2025_1_9 16：25：41 | | -CSDN博客 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 中断 | | saved date: Thu Jan 09 2025 16:25:41 GMT+0800 (中国标准时间) | |
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| _2024_12_23_12：06：15_ | 2024_12_23 12：06：15 | | 概述-CSDN博客 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 中断 | | saved date: Mon Dec 23 2024 12:06:15 GMT+0800 (中国标准时间) | |
| _2025_1_9_16：26：29_ | 2025_1_9 16：26：29 | | -CSDN博客 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 中断 | | saved date: Thu Jan 09 2025 16:26:29 GMT+0800 (中国标准时间) | |
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| _2025-05-27_14：56：03_ | 2025-05-27 14：56：03 | | tech-fast-int@lists.riscv.org _ Home | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 中断 | | Summary: The Fast Interrupt Task Group aims to create a low-latency, vectored, priority-based, preemptive interrupt scheme for a single RISC-V Hart. This design adheres to RISC-V standards and includes both hardware specifications and software Application Binary Interfaces (ABIs)/Application Programming Interfaces (APIs). Compiler conventions for annotating interrupt handler functions will also be standardized.Fast Interrupt Task Group 旨在为单个 RISC-V Hart 创建一个低延迟、矢量化、基于优先级的抢占式中断方案。此设计符合 RISC-V 标准，包括硬件规范和软件应用程序二进制接口 （ABI）/应用程序编程接口 （API）。用于注释中断处理程序函数的编译器约定也将标准化。 | |
| _中断_risc-v_ | 中断 risc-v | | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 中断 | | saved date: Fri Jan 17 2025 15:59:12 GMT+0800 (中国标准时间) | |
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| _2024_10_25_17_31_22_ | 2024_10_25 17_31_22 | | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 中断 用户态中断 | | saved date: Fri Oct 25 2024 17:31:22 GMT+0800 (中国标准时间) | |
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| _2025-03-10_17：25：48_ | 2025-03-10 17：25：48 | | HotChips 2023_ Ventana 不寻常的 Veyron V1 - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 产品 | | Summary: This article discusses Ventana's unconventional Veyron V1 CPU design, focusing on its unique features. The Veyron V1 is an eight-way out-of-order core with a 15-cycle branch mispredict penalty and a large 12K item single-level BTB and a "single-cycle next-line predictor." It also has a 512KB L1/L2 instruction cache and a 64KB VIVT data cache. The design aims for a 3.6GHz target frequency but can be scaled down to reduce power consumption. The article also mentions Ventana's plans to improve the branch mispredict penalty in the V2 architecture. The article was originally published on ChipsAndCheese and is translated and adapted here with permission from the author.本文讨论了 Ventana 非常规的 Veyron V1 CPU 设计，重点介绍其独特的功能。威龙 V1 是一个八向乱序内核，具有 15 个周期的分支错误预测惩罚和一个大型 12K 项单级 BTB 和一个“单周期下线预测器”。它还具有 512KB L1/L2 指令缓存和 64KB VIVT 数据缓存。该设计的目标是 3.6GHz 的目标频率，但可以缩小以降低功耗。文章还提到了 Ventana 改进 V2 架构中分支错误预测惩罚的计划。本文最初发表在 ChipsAndCheese 上，经作者许可在此处翻译和改编。 | |
| _2025-03-10_17：02：13_ | 2025-03-10 17：02：13 | | RISC-V最先进CPU微架构分析_rva23 profile-CSDN博客 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 产品 | | Summary: The blog post discusses the advanced CPU microarchitectures of SIFIVE P870 and Veyron V1, both of which are based on the RISC-V instruction set. SIFIVE P870 follows the RV32GC profile and features a 6-decode processor, 96-entry integer issue queue, and 64KB L1/L2 instruction cache. Veyron V1 targets the server and automotive markets and has a 64KB Dcache, 512KB L1/L2 instruction cache, and a 2-cycle Icache and ITLB access delay. Both microarchitectures have a similar instruction set and have a similar number of integer and FP floating-point instructions. However, SIFIVE P870 has a deeper pipeline, which puts more pressure on the predictor and requires more power consumption. Veyron V1 has a more power-efficient design and a larger L2 TLB. Overall, both microarchitectures aim to provide high performance and low power consumption for their respective markets.该博客文章讨论了 SIFIVE P870 和 Veyron V1 的高级 CPU 微架构，这两者都基于 RISC-V 指令集。SIFIVE P870 遵循 RV32GC 配置文件，具有 6 解码处理器、96 条目整数发出队列和 64KB L1/L2 指令缓存。Veyron V1 面向服务器和汽车市场，具有 64KB Dcache、512KB L1/L2 指令缓存以及 2 周期 Icache 和 ITLB 访问延迟。两种微架构具有相似的指令集，并且具有相似数量的整数和 FP 浮点指令。但是，SIFIVE P870 具有更深的管道，这给预测器带来了更大的压力，并且需要更多的功耗。威龙 V1 具有更节能的设计和更大的 L2 TLB。总体而言，这两种微架构都旨在为各自的市场提供高性能和低功耗。 | |
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| _2025-04-02_11：47：19_ | 2025-04-02 11：47：19 | | Semidynamics - About us | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 企业 | | Summary: Semidynamics is a European RISC-V IP core provider based in Barcelona, specializing in high-bandwidth, high-performance, vector unit IP cores for machine learning and AI applications. The company, founded in 2016, has a team of experienced hardware and software engineers, and offers services from specification to design and validation. They also provide employee development services, both on-site and remotely. The team includes executives Roger, Pedro, Silvana, Bruno, Laura, Marc, Volker, Clara, Federico, Deepak, Usman, Todor, Jordi, Shyamkumar, Karel, Francesco, Chetan, Kevin, Muhammad, Joan, Ismael, Arnau, Stefano, Aitor, Àlex, Ian, Shreeharsha, Hector, Florencia, Martí, Branimir, Jaume, Zeeshan, José, Pia, Enric, and many others. Semidynamics is a member of RISC-V International, a global non-profit organization, and collaborates with various institutions and grants, including the European Processor Initiative (EPI) and MontBlanc 2020 project. They are also developing a RISC-V cloud server architecture, called RISER, and a cloud service, Vitamin-V, based on open-source RISC-V technology. Semidynamics offers customized high-bandwidth RISC-V IP cores for your next project. Contact them for more information.Semidynamics 是一家总部位于巴塞罗那的欧洲 RISC-V IP 核提供商，专门为机器学习和 AI 应用提供高带宽、高性能的矢量单元 IP 核。该公司成立于 2016 年，拥有一支经验丰富的硬件和软件工程师团队，提供从规范到设计和验证的服务。他们还提供现场和远程员工发展服务。该团队包括高管 Roger、Pedro、Silvana、Bruno、Laura、Marc、Volker、Clara、Federico、Deepak、Usman、Todor、Jordi、Shyamkumar、Karel、Francesco、Chetan、Kevin、Muhammad、Joan、Ismael、Arnau、Stefano、Aitor、Àlex、Ian、Shreeharsha、Hector、Florencia、Martí、Branimir、Jaume、Zeeshan、José、Pia、Enric 等。Semidynamics 是全球非营利组织 RISC-V International 的成员，并与各种机构和赠款合作，包括欧洲处理器倡议 （EPI） 和 MontBlanc 2020 项目。他们还在开发一种名为 RISER 的 RISC-V 云服务器架构，以及一种基于开源 RISC-V 技术的云服务 Vitamin-V。Semidynamics 为您的下一个项目提供定制的高带宽 RISC-V IP 内核。请联系他们以获取更多信息。 | |
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| _2025-05-28_15：16：14_ | 2025-05-28 15：16：14 | | 蓝芯算力 _ 项目信息-36氪 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 企业 | | Summary: Established in May 2023, this company focuses on designing high-performance chipsets and specializes in the research and design of RISC-V architecture server CPUs. They offer self-controlled solutions for data centers, cloud computing, enterprise applications (including finance, securities, insurance, telecommunications, etc.), AI and big data, big models, and other applications in China. The core team and R&D staff have extensive experience working in international tech giants (Intel, Qualcomm, etc.) and a track record of delivering multiple CPU products. They have signed long-term strategic partnerships with renowned RISC-V research institutions and domestic server product manufacturers and are currently pushing forward with CPU product development according to plan.该公司成立于 2023 年 5 月，专注于设计高性能芯片组，专门从事 RISC-V 架构服务器 CPU 的研究和设计。他们为中国的数据中心、云计算、企业应用（包括金融、证券、保险、电信等）、人工智能和大数据、大数据和其他应用提供自主解决方案。核心团队和研发人员在国际科技巨头（英特尔、高通等）有丰富的工作经验，并有交付多种 CPU 产品的记录。他们与著名的 RISC-V 研究机构和国内服务器产品制造商签署了长期战略合作伙伴关系，目前正在按计划推进 CPU 产品开发。 | |
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| _2025-05-27_11：13：30_ | 2025-05-27 11：13：30 | | RISC-V Summit Europe 2025 - Welcome | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 会议 | | Summary: The RISC-V Summit Europe is a premier event connecting European industry, government, research, academia, and ecosystem support to build the future of innovation on RISC-V. RISC-V is an open standard instruction set architecture (ISA) that has gained significant success in Europe, with one-third of its global community based in the region. The summit takes place in Paris from May 12-15, 2025, and aims to help attendees explore both commercial and research applications. The event features keynotes, invited talks, and sessions on topics such as high-performance RISC-V systems, open chiplet architecture, and RISC-V in space computing.RISC-V 欧洲峰会是连接欧洲工业、政府、研究、学术界和生态系统支持的首要活动，旨在构建 RISC-V 创新的未来。RISC-V 是一种开放标准指令集架构 （ISA），在欧洲取得了重大成功，其全球社区的三分之一位于该地区。该峰会将于 2025 年 5 月 12 日至 15 日在巴黎举行，旨在帮助与会者探索商业和研究应用。该活动包括主题演讲、特邀报告和会议，主题包括高性能 RISC-V 系统、开放式小芯片架构和空间计算中的 RISC-V。 | |
| _2025-03-07_17：48：43_ | 2025-03-07 17：48：43 | | RISC-V Day Tokyo｜阎明铸分享SAIL-RISCV内存模型重构 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 内存 | | Summary: At the RISC-V Day Tokyo 2025 Spring event, Hening Chang from the RUYISDK team at the Chinese Academy of Sciences Software Research Institute shared their achievements in restructuring the SAIL-RISCV memory model. They presented a poster on the challenges of SAIL-RISCV's memory model, which includes the lack of support for 34-bit physical addresses and the ambiguity between physical and virtual memory. The team addressed these challenges by restructuring the SAIL-RISCV memory model, enabling 34-bit physical address support and ensuring type safety. The improved memory model offers better flexibility, reduces coupling between physical and virtual memory, and provides a more precise memory abstraction for SAIL-RISCV. Hening Chang also emphasized the importance of continuous technological development and innovation in the RISC-V ecosystem.在 RISC-V Day 东京 2025 春季活动中，来自中科院软件研究所 RUYISDK 团队的 Hening Chang 分享了他们在重构 SAIL-RISCV 内存模型方面的成就。他们展示了一张关于 SAIL-RISCV 内存模型挑战的海报，其中包括缺乏对 34 位物理地址的支持以及物理内存和虚拟内存之间的歧义。该团队通过重构 SAIL-RISCV 内存模型、启用 34 位物理地址支持和确保类型安全来应对这些挑战。改进的内存模型提供了更好的灵活性，减少了物理内存和虚拟内存之间的耦合，并为 SAIL-RISCV 提供了更精确的内存抽象。张海宁还强调了 RISC-V 生态系统中持续技术发展和创新的重要性。 | |
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| _2025-03-18_11：50：25_ | 2025-03-18 11：50：25 | | riscv_ Introduce 64K base page [LWN.net] | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 内存 | | Summary: This email contains a patch series for introducing a larger base page size on RISC-V architecture, which currently only supports 4K pages. The patch aims to decouple software pages managed by the kernel from hardware pages managed by the MMU, allowing larger software base pages and reducing TLB misses. The patch series includes adaptations to various architecture codes and page table operations, and supports both bare metal and virtualization scenarios. Future work includes reducing memory usage, implementing isolation measures, and collaborating with folios, among other things. The patch series is based on v6.7-rc1 and contains changes to multiple files in the RISC-V kernel codebase.此电子邮件包含一个补丁系列，用于在 RISC-V 架构上引入更大的基本页面大小，该架构目前仅支持 4K 页面。该补丁旨在将内核管理的软件页面与 MMU 管理的硬件页面分离，从而允许更大的软件基本页面并减少 TLB 缺失。补丁系列包括对各种架构代码和页表作的适配，同时支持裸机和虚拟化场景。未来的工作包括减少内存使用、实施隔离措施以及与作品集协作等。补丁系列基于 v6.7-rc1，包含对 RISC-V 内核代码库中多个文件的更改。 | |
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| _2025-03-18_18：41：39_ | 2025-03-18 18：41：39 | | [PATCH v10 1_1] riscv_ Allow to downgrade paging mode from the command line - Alexandre Ghiti | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 内存 satp | | Summary: This is an email discussing a patch for the RISC-V Linux kernel that adds two early command line parameters to allow downgrading the satp (Supervisor Access Control Tags) mode from the command line. The patch also includes modifications to the kernel build system and various source files to support these new parameters. The patch was tested and reviewed by Björn Töpel.这是一封讨论 RISC-V Linux 内核补丁的电子邮件，该补丁添加了两个早期命令行参数，以允许从命令行降级 satp（主管访问控制标签）模式。该补丁还包括对内核构建系统和各种源文件的修改，以支持这些新参数。该补丁由 Björn Töpel 进行测试和审查。 | |
| _2025-03-06_12：01：19_ | 2025-03-06 12：01：19 | | 如何理解RISC-V中的hart_ - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | Summary: The term "hart" is used in the context of RISC-V to represent an abstract execution resource, as opposed to a software thread programming abstraction. It is a hardware thread and operates like an independent hardware thread from the perspective of software inside an execution environment. An execution environment can time-multiplex a set of guest harts onto fewer host harts, but they must operate independently and the environment must be able to preempt guest harts and not wait indefinitely for guest software to yield control. In simple terms, a hart is a hardware thread, similar to any other architecture's hardware thread. The difference between RISC-V cores and harts is the same as that between other architectures' cores and hardware threads - there is nothing new here. However, the concept of a hart can be implemented directly in hardware or virtualized, and it is a resource within an execution environment that has state and advances along executing a RISC-V instruction stream independently of other software inside the same execution environment.在 RISC-V 的上下文中，术语 “hart” 用于表示抽象执行资源，而不是软件线程编程抽象。它是一个硬件线程，从执行环境中的软件角度来看，它的运行方式类似于独立的硬件线程。执行环境可以将一组客户机 HART 定时多路复用到较少的主机 HART 上，但它们必须独立运行，并且环境必须能够抢占客户机 HART 并且不能无限期地等待客户机软件获得控制权。简单来说，HART 是一种硬件线程，类似于任何其他架构的硬件线程。RISC-V 核心和 harts 的区别与其他架构的 core 和硬件线程的区别相同——这里没有什么新鲜的。然而，HART 的概念可以直接在硬件中实现，也可以虚拟化实现，它是执行环境中的一种资源，在执行 RISC-V 指令流的过程中具有状态和进度，独立于同一执行环境中的其他软件。 | |
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| _2024_11_14_12_47_30_ | 2024_11_14 12_47_30 | | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 安全 | | saved date: Thu Nov 14 2024 12:47:30 GMT+0800 (中国标准时间) | |
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| _2024_11_25_17：32：40_ | 2024_11_25 17：32：40 | | 开源芯片与RISC-V - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | saved date: Mon Nov 25 2024 17:32:40 GMT+0800 (中国标准时间) | |
| _2025-04-18_19：20：44_ | 2025-04-18 19：20：44 | | RISC-V on the Performance Top _ Performance Blog | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 性能 | | Summary: This text consists of several blog posts by Fei Wu discussing various topics related to RISC-V, including its performance, vector extensions on Valgrind, the importance of frame pointers, implicit type conversions causing panics, Git bisect for debugging, RISC-V interrupt handling, challenges and advantages of RISC-V, and RISC-V syscall performance regression. The posts also mention testing results and commands used for analysis.本文由 Fei Wu 的几篇博客文章组成，讨论了与 RISC-V 相关的各种主题，包括其性能、Valgrind 上的向量扩展、帧指针的重要性、导致 panic 的隐式类型转换、用于调试的 Git bisect、RISC-V 中断处理、RISC-V 的挑战和优势以及 RISC-V 系统调用性能回归。这些帖子还提到了用于分析的测试结果和命令。 | |
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| _2025-04-20_15：30：19_ | 2025-04-20 15：30：19 | | 6.S081 _ Fall 2021 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 操作系统 | | Summary: This text provides a schedule for the MIT 6.S081: Operating System Engineering course, including lecture topics, preparation assignments, and homework due dates. The course covers various aspects of operating systems, such as system calls, page tables, scheduling, file systems, and virtual memory. Students are expected to attend lectures, read assigned materials, and complete homework assignments. The schedule also includes some holidays and breaks throughout the semester.本文提供了 MIT 6.S081：作系统工程课程的时间表，包括讲座主题、准备作业和家庭作业截止日期。该课程涵盖作系统的各个方面，例如系统调用、页表、调度、文件系统和虚拟内存。学生需要参加讲座、阅读指定的材料并完成家庭作业。该时间表还包括整个学期的一些假期和休息时间。 | |
| _2025-04-20_15：22：48_ | 2025-04-20 15：22：48 | | MIT 6.S081_ Operating System Engineering - CS自学指南 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 操作系统 | | Summary: This is an introduction to MIT 6.S081: Operating System Engineering, a course offered at the Massachusetts Institute of Technology (MIT). The course is taught by professors who developed the operating system JOS and have now created a new one called xv6 based on RISC-V. The course requires a solid foundation in system architecture, C language, and RISC-V assembly language. The course material is primarily in C and RISC-V, and its difficulty level is rated as five stars. The estimated study time is 150 hours. | |
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| _2024_8_27_12_57_15_ | 2024_8_27 12_57_15 | | 时代在召唤RISC-V | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | saved date: Tue Aug 27 2024 12:57:15 GMT+0800 (中国标准时间) | |
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| _2025-04-14_15：51：22_ | 2025-04-14 15：51：22 | | RISC-V架构下外设虚拟化解决方案 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 IO | | Summary: RISC-V architecture introduced IOMMU to address DMA transfer performance issues in virtual machines. IOMMU provides GPA to SPA address translation ability for each DMA device through a device table. With IOMMU, the DMA data transfer process can be automatically handled by the hardware, reducing the need for hypervisor OS to capture every DMA transfer. Additionally, IOMMU allows CPU and DMA to share the same process table, enabling VUs user processes to use DMA directly. For DMA devices with IOVA to GPA remapping, such as GPUs, IOMMU's process table can be used for automatic IOVA to GPA to SPA address translation. RISC-V's IOMMU supports PCIe's ATS and PRI interfaces, allowing for optimized MSI address translation for PCIe devices. (图1 - IOMMU下的两级地址翻译) | |
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| _2025-03-20_16：47：51_ | 2025-03-20 16：47：51 | | RISC-V AIA support for RISC-V machines — QEMU documentation | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: The input describes the implementation of Advanced Interrupt Architecture (AIA) support in the virtRISC-V machine for TCG and KVM accelerators. There are two main modes: "aia=aplic" and "aia=aplic-imsic". The former adds one or more APLIC (Advanced Platform Level Interrupt Controller) devices, while the latter adds one or more APLIC devices and an IMSIC (Incoming MSI Controller) device for each CPU. The user behavior remains the same regardless of the accelerator used, but the emulated components change between userspace and kernel space depending on the accelerator. When running TCG, all controllers are emulated in userspace, while KVM provides no m-mode, resulting in no m-mode APLIC or IMSIC emulation. The table provided outlines how the AIA and accelerator options determine what is emulated in userspace.输入描述了 virtRISC-V 机器中对 TCG 和 KVM 加速器的高级中断架构 （AIA） 支持的实现。有两种主要模式：“aia=aplic”和“aia=aplic-imsic”。前者为每个 CPU 添加一个或多个 APLIC （高级平台级中断控制器） 设备，而后者为每个 CPU 添加一个或多个 APLIC 设备和一个 IMSIC （传入 MSI 控制器） 设备。无论使用何种加速器，用户行为都保持不变，但仿真组件在用户空间和内核空间之间会发生变化，具体取决于加速器。运行 TCG 时，所有控制器都在用户空间中仿真，而 KVM 不提供 m 模式，因此没有 m 模式 APLIC 或 IMSIC 仿真。提供的表格概述了 AIA 和 accelerator 选项如何确定在用户空间中模拟的内容。 | |
| _2025-03-20_16：50：26_ | 2025-03-20 16：50：26 | | RISC-V IOMMU support for RISC-V machines — QEMU documentation | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: This text describes the implementation of RISC-V IOMMU (Input/Output Memory Management Unit) emulation in QEMU (Quick Emulator) version 9.2.90. The emulation includes a PCI reference device (riscv-iommu-pci) and a platform bus device (riscv-iommu-sys) for RISC-V machines. The PCI device can be added to the 'virt' RISC-V machine using the command line option '-device riscv-iommu-pci'. The IOMMU behavior is defined by the spec but its operation is OS dependent, with the current Linux kernel support (linux-v8) not yet fully feature-complete. The IOMMU emulation was tested using the Ventana Micro Systems kernel repository, which includes patches for KVM VFIO passthrough with irqbypass. The riscv-iommu-pci device can be configured with options such as bus, ioatc-limit, intremap, ats, off, s-stage, and g-stage. The riscv-iommu-sys device is implemented as a platform bus device for RISC-V boards and can be enabled using the 'iommu-sys' machine option.本文描述了 QEMU （Quick Emulator） 版本 9.2.90 中 RISC-V IOMMU （输入/输出内存管理单元） 仿真的实现。仿真包括用于 RISC-V 计算机的 PCI 参考设备 （riscv-iommu-pci） 和平台总线设备 （riscv-iommu-sys）。可以使用命令行选项 '-device riscv-iommu-pci' 将 PCI 设备添加到 'virt' RISC-V 机器上。IOMMU 行为由规范定义，但其作取决于作系统，当前的 Linux 内核支持 （linux-v8） 尚未完全完成功能。IOMMU 仿真使用 Ventana Micro Systems 内核存储库进行了测试，其中包括使用 irqbypass 的 KVM VFIO 直通补丁。riscv-iommu-pci 设备可以配置 bus、ioatc-limit、intremap、ats、off、s-stage 和 g-stage 等选项。riscv-iommu-sys 设备是作为 RISC-V 板的平台总线设备实现的，可以使用 'iommu-sys' 机器选项启用。 | |
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| _2025-04-22_14：43：19_ | 2025-04-22 14：43：19 | | RISC-V嵌套虚拟化支持 - 允许Hypervisor上运行Hypervisor_哔哩哔哩_bilibili | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: This page discusses the support for RISC-V nested virtualization, which enables the running of a hypervisor on another hypervisor, referred to as the "nested hypervisor," at the guest level on the first hypervisor. This architecture allows for increased security and efficiency in virtualized systems.本页讨论了对 RISC-V 嵌套虚拟化的支持，它允许在第一个虚拟机管理程序的来宾级别在另一个虚拟机管理程序（称为“嵌套虚拟机管理程序”）上运行虚拟机管理程序。此体系结构可以提高虚拟化系统的安全性和效率。 | |
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| _2025-05-23_15：01：36_ | 2025-05-23 15：01：36 | | [PULL 12_22] riscv_ Allow user to set the satp mode | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 qemu satp | | Summary: This is a series of commit messages from the RISC-V QEMU project. The commits introduce various changes to the RISC-V CPU implementation in QEMU. Some of the changes include: | |
| _2025-05-09_14：46：54_ | 2025-05-09 14：46：54 | | sig-qemu@lists.riscv.org _ RVA23 profile support | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 qemu | | Summary: A group discussion on the RVA23 profile support for QEMU is taking place on the sig-qemu list. The new RVA23 profile, which includes mandatory extensions Ss1p13, Zimop, Zcmop, Supm, Ssnpm, Shgatpa, Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, and Shvsatpa, and optional extensions Zabha, Ziccamoc, Zama16b, Sdex, Ssstrict, Svvptc, and Sspm, is being discussed. The group members are encouraging each other to implement these extensions on QEMU and update the progress on the group.关于 RVA23 配置文件对 QEMU 支持的小组讨论正在 sig-qemu 列表中进行。新的 RVA23 配置文件，包括强制性扩展 Ss1p13、Zimop、Zcmop、Supm、Ssnpm、Shgatpa、Ssstateen、Shcounterenw、Shvstvala、Shtvala、Shvstvecd 和 Shvsatpa，以及可选扩展 Zabha、Ziccamoc、Zama16b、Sdex、Ssstrict、Svvptc 和 Sspm，正在讨论中。小组成员互相鼓励在 QEMU 上实施这些扩展，并更新小组的进展。 | |
| _2025-03-10_15：36：23_ | 2025-03-10 15：36：23 | | riscv kvm 方案代码调研 _ blog | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: This text describes the virtualization of memory, CPU, timer, and interrupts in the context of a virtual machine using KVM (Kernel-based Virtual Machine) for RISC-V processors. The memory virtualization includes the conversion from Guest Physical Address (GPA) to Host Physical Address (HVA), with sub-steps for data structures and process analysis. The CPU virtualization involves the VCPU execution flow, including KVM_VCPU_RUN, vCPU scheduling, and hs timer tick details. The timer virtualization includes RISC-V timer support, user-level access, guest access with guest timer tick processing and guest time, and sstc vstimecmp. Interrupt virtualization includes PIC interrupt injection with registration and triggering processes, and AIA imsic interrupt processing with kvm_riscv_vcpu_aia_update, guest access to siselect and sireg, MMIO injection, and imsic doorbell interrupt.本文描述了使用 KISC-V 处理器的 KVM（基于内核的虚拟机）在虚拟机环境中对内存、CPU、定时器和中断进行虚拟化。内存虚拟化包括从来宾物理地址 （GPA） 到主机物理地址 （HVA） 的转换，以及用于数据结构和进程分析的子步骤。CPU 虚拟化涉及 VCPU 执行流程，包括 KVM_VCPU_RUN、vCPU 调度和 hs 计时器 tick 详细信息。计时器虚拟化包括 RISC-V 计时器支持、用户级访问、使用来宾计时器时钟周期处理和来宾时间的来宾访问以及 sstc vstimecmp。中断虚拟化包括带有注册和触发进程的 PIC 中断注入、带有 kvm_riscv_vcpu_aia_update 的 AIA imsic 中断处理、来宾对 siselect 和 sireg 的访问、MMIO 注入和 imsic 门铃中断。 | |
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| _2025-04-11_14：07：01_ | 2025-04-11 14：07：01 | | riscv_ KVM_ Remove unnecessary vcpu kick - kernel_git_riscv_linux.git - RISC-V Linux kernel tree | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: The RISC-V Linux kernel tree had a commit on February 21, 2025, by Bill Xiang, which removed an unnecessary vCPU kick after writing to the vs\_file in kvm\_riscv\_vcpu\_aia\_imsic\_inject. This change is applicable for vCPUs that are running and have their interrupts forwarded directly as an MSI. For vCPUs that are descheduled after emulating WFI, the guest external interrupt is enabled, causing the writing to the vs\_file to cause a guest external interrupt and wake up the vCPU in hgei\_interrupt to handle the interrupt properly. The commit was reviewed by Andrew Jones and Radim Krčmář and signed off by Anup Patel. The diff shows one deletion in arch/riscv/kvm/aia\_imsic.c.RISC-V Linux 内核树于 2025 年 2 月 21 日由 Bill Xiang 提交，该提交在写入 kvm\_riscv\_vcpu\_aia\_imsic\_inject 中的 vs\_file 后删除了不必要的 vCPU 踢出。此更改适用于正在运行且其中断作为 MSI 直接转发的 vCPU。对于在模拟 WFI 后取消调度的 vCPU，将启用客户机外部中断，从而导致对 vs\_file 的写入导致客户机外部中断，并唤醒 hgei\_interrupt 中的 vCPU 以正确处理中断。该提交由 Andrew Jones 和 Radim Krčmář 审查，并由 Anup Patel 签署。差异显示 arch/riscv/kvm/aia\_imsic.c 中的一个删除。 | |
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| _2025-04-03_10：20：36_ | 2025-04-03 10：20：36 | | 中国科学院软件研究所团队推动 Cloud Hypervisor 官方支持 RISC-V | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: The Chinese Academy of Sciences Software Research Institute team has officially released Cloud-Hypervisor v45.0, which adds experimental RISC-V support. This makes Cloud-Hypervisor the first lightweight virtualization solution to integrate with Kata-containers and fully support RISC-V. The update received attention in the overseas open-source community, with Phoronix reporting on its significance as the first step for RISC-V in the server virtualization domain. Cloud-Hypervisor, built using the Rust programming language, aims to create a complete Rust virtualization software ecosystem for future RISC-V chips. As the bridge connecting the KVM virtualization engine with upper-layer applications, Cloud-Hypervisor is a crucial implementation in the RISC-V virtualization software landscape. It provides a runtime environment for Kubernetes and other container orchestration systems with virtual machine-level isolation, enhancing security while implementing flat fault/performance isolation within clusters. Cloud-Hypervisor, a modern, lightweight, and cross-platform virtualization monitoring program, has been developed over five years and has contributed significantly to the RISC-V community, ranking ninth in total contributions and first in RISC-V contributions globally. To achieve Cloud Hypervisor's RISC-V support, the team focused on three core areas: 1) virtualization core capabilities, 2) engineering system upgrades, and 3) production-level stability assurance. These efforts have led to the initial support of hypervisor, arch, vm-allocator, devices, and vmm modules on the RISC-V architecture. The team plans to further enhance Cloud-Hypervisor's RISC-V architecture support by addressing the feature differences between RISC-V, x86, and ARM, completing FDT generation links, adding UEFI boot support, and supporting PMU, IOMMU, and TPM devices. OpenEuler, as the first verification platform for RISC-V virtualization capabilities, will continue to support Cloud-Hypervisor on the openEuler platform and integrate it with the Kata Containers secure container technology path, creating a secure container infrastructure based on openEuler RISC-V. The release of Cloud-Hypervisor v45.0 marks a significant milestone in the RISC-V virtualization roadmap. By implementing systemic breakthroughs in instruction register operations, AIA interrupt controller integration, and memory management, the team is building a virtualization ability matrix that conforms to the RVA23 specification. This achievement not only provides a verified RISC-V virtualization implementation baseline for the open-source community but also lays the foundation for the standardized evolution of future RISC-V virtualization-related software, enabling RISC-V server ecosystems to possess software validation capabilities from chip features to container runtimes even before the hardware platform matures.中国科学院软件研究院团队正式发布 Cloud-Hypervisor v45.0，增加了实验性的 RISC-V 支持。这使得 Cloud-Hypervisor 成为第一个与 Kata 容器集成并完全支持 RISC-V 的轻量级虚拟化解决方案。该更新受到了海外开源社区的关注，Phoronix 报告了其作为 RISC-V 在服务器虚拟化领域的第一步的重要性。Cloud-Hypervisor 使用 Rust 编程语言构建，旨在为未来的 RISC-V 芯片创建一个完整的 Rust 虚拟化软件生态系统。作为连接 KVM 虚拟化引擎与上层应用程序的桥梁，Cloud-Hypervisor 是 RISC-V 虚拟化软件领域中的关键实现。它为 Kubernetes 和其他容器编排系统提供了一个具有虚拟机级隔离的运行时环境，在增强安全性的同时在集群内实施平面故障/性能隔离。Cloud-Hypervisor 是一个现代、轻量级和跨平台的虚拟化监控程序，已经开发了五年多，为 RISC-V 社区做出了重大贡献，在全球总贡献中排名第九，在 RISC-V 贡献中排名第一。为了实现 Cloud Hypervisor 的 RISC-V 支持，该团队专注于三个核心领域：1） 虚拟化核心能力，2） 工程系统升级，以及 3） 生产级稳定性保证。这些努力导致了对 RISC-V 架构上的 hypervisor、arch、vm-allocator、devices 和 vmm 模块的初步支持。 该团队计划通过解决 RISC-V、x86 和 ARM 之间的功能差异，完成 FDT 生成链接，添加 UEFI 启动支持，并支持 PMU、IOMMU 和 TPM 设备，进一步增强 Cloud-Hypervisor 的 RISC-V 架构支持。OpenEuler 作为首个 RISC-V 虚拟化能力的验证平台，将继续在 openEuler 平台上支持 Cloud-Hypervisor，并与 Kata Containers 安全容器技术路径集成，打造基于 openEuler RISC-V 的安全容器基础设施。Cloud-Hypervisor v45.0 的发布标志着 RISC-V 虚拟化路线图中的一个重要里程碑。通过在指令寄存器作、AIA 中断控制器集成和内存管理方面实现系统性突破，该团队正在构建符合 RVA23 规范的虚拟化能力矩阵。这一成果不仅为开源社区提供了经过验证的 RISC-V 虚拟化实现基线，也为未来 RISC-V 虚拟化相关软件的标准化演进奠定了基础，使 RISC-V 服务器生态系统在硬件平台成熟之前就拥有从芯片特性到容器运行时的软件验证能力。 | |
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| _2025-03-27_11：31：09_ | 2025-03-27 11：31：09 | | riscv_ KVM_ Remove unnecessary vcpu kick - kernel_git_riscv_linux.git - RISC-V Linux kernel tree | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 中断 | | Summary: The RISC-V Linux kernel tree had a commit on February 21, 2025, by Bill Xiang, which removed an unnecessary vCPU kick after writing to the vs\_file in kvm\_riscv\_vcpu\_aia\_imsic\_inject. This change is applicable for vCPUs that are running and have their interrupts forwarded directly as an MSI. For vCPUs that are descheduled after emulating WFI, the guest external interrupt is enabled, causing the writing to the vs\_file to cause a guest external interrupt and wake up the vCPU in hgei\_interrupt to handle the interrupt properly. The commit was reviewed by Andrew Jones and Radim Krčmář and signed off by Anup Patel. The diff shows one deletion in arch/riscv/kvm/aia\_imsic.c.RISC-V Linux 内核树于 2025 年 2 月 21 日由 Bill Xiang 提交，该提交在写入 kvm\_riscv\_vcpu\_aia\_imsic\_inject 中的 vs\_file 后删除了不必要的 vCPU 踢出。此更改适用于正在运行且其中断作为 MSI 直接转发的 vCPU。对于在模拟 WFI 后取消调度的 vCPU，将启用客户机外部中断，从而导致对 vs\_file 的写入导致客户机外部中断，并唤醒 hgei\_interrupt 中的 vCPU 以正确处理中断。该提交由 Andrew Jones 和 Radim Krčmář 审查，并由 Anup Patel 签署。差异显示 arch/riscv/kvm/aia\_imsic.c 中的一个删除。 | |
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| _2025-05-14_10：39：52_ | 2025-05-14 10：39：52 | | riscv_ KVM_ Remove unnecessary vcpu kick · torvalds_linux@d252435 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 中断 | | Summary: A GitHub page displays information about a commit in the Linux kernel project. The commit, made by Bill Xiang, removes an unnecessary vCPU kick in the riscv: KVM (Kernel-based Virtual Machine) code. The vCPU kick is no longer needed when writing to the vs\_file directly forwards an interrupt as an MSI to the vCPU. The commit also modifies the handling of guest external interrupts. The changes were reviewed by Andrew Jones and Radim Krčmář.GitHub 页面显示有关 Linux 内核项目中提交的信息。由 Bill Xiang 提交的提交删除了 riscv： KVM（基于内核的虚拟机）代码中不必要的 vCPU 踢出。写入 vs\_file 将中断作为 MSI 直接转发到 vCPU 时，不再需要 vCPU 踢出。该提交还修改了客户机外部中断的处理。Andrew Jones 和 Radim Krčmář 审查了这些更改。 | |
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| _2024_8_30_20_18_48_ | 2024_8_30 20_18_48 | | 项目概述 _ 一生一芯 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v | | saved date: Fri Aug 30 2024 20:18:48 GMT+0800 (中国标准时间) | |
| _2025-06-19_14：36：38_ | 2025-06-19 14：36：38 | | 香山开源处理器用户手册 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 香山 | | Summary: This document is the user manual for the XiangShan open source processor, specifically for the Kunming Lake V2R2. The latest version of the document can be obtained from the provided links: web version - , PDF file - . The document is licensed under CC BY 4.0 and is subject to the terms of the license. The document provides preliminary information and may be updated irregularly. No warranties are given for the statements, information, or suggestions in the document. | |
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| _2024_8_29_14_42_03_ | 2024_8_29 14_42_03 | | 一生一芯 | | 原文链接失效了?试试备份 | | TAGs:处理器 | | saved date: Thu Aug 29 2024 14:42:03 GMT+0800 (中国标准时间) | |
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| _2024_10_25_16_21_51_ | 2024_10_25 16_21_51 | | | 原文链接失效了?试试备份 | | TAGs:处理器 中断 用户态中断 | | saved date: Fri Oct 25 2024 16:21:51 GMT+0800 (中国标准时间) | |
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| _2025-04-09_11：38：32_ | 2025-04-09 11：38：32 | | SMMU跟TrustZone啥关系？ - 极术社区 - 连接开发者与智能计算生态 | | 原文链接失效了?试试备份 | | TAGs:处理器 安全 | | Summary: This text discusses the relationship between SMMU (System Memory Management Unit) and TrustZone in the context of securing access to memory for various masters in a system. TrustZone is a security mechanism that partitions system resources into secure and non-secure parts, and SMMU is a System IP that allows other masters to use memory with a similar structure to the CPU's MMU. By adding SMMU, other masters can have MMU functionality, which includes address translation, memory protection, and isolation. This allows for more secure access to memory and better control over what each master can access. The text also mentions that SMMUv1, SMMUv2, and SMMUv3 have different architectures, programming methods, and hardware implementations but serve similar purposes.本文讨论了 SMMU （System Memory Management Unit） 和 TrustZone 在保护系统中各种主控对内存的访问的上下文中的关系。TrustZone 是一种安全机制，将系统资源划分为安全和不安全部分，而 SMMU 是一个系统 IP，允许其他主控使用结构与 CPU 的 MMU 类似的内存。通过添加 SMMU，其他主控可以具有 MMU 功能，包括地址转换、内存保护和隔离。这允许更安全地访问内存，并更好地控制每个主控可以访问的内容。正文还提到 SMMUv1、SMMUv2 和 SMMUv3 具有不同的体系结构、编程方法和硬件实现，但用途相似。 | |
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| _2025-04-09_11：38：10_ | 2025-04-09 11：38：10 | | TrustZone是如何支持安全中断的？ - 极术社区 - 连接开发者与智能计算生态 | | 原文链接失效了?试试备份 | | TAGs:处理器 安全 | | Summary: TrustZone is a system-level security solution that can be implemented in SoC chips using a CPU that supports TrustZone and specific features such as secure address space filtering, secure timers, secure clocks, secure interrupts, key management, secure ROM code, secure debug, and secure SRAM. TrustZone allows easy management of peripherals, including access permissions, master control for secure and non-secure access, and secure interrupt generation and CPU response. This text discusses how to generate secure interrupts in TrustZone, involving secure peripherals, GIC, and the CPU. While GIC is often overlooked, understanding how TrustZone supports secure interrupts is crucial for resolving related issues. The CPU supports secure interrupts by checking if they are masked and determining where to process them. The processing of the interrupt depends on the EL level and exception handler. GIC supports secure interrupts by grouping them and securing related registers, allowing the CPU to configure them only when in a secure state. In GICv3, three groups are used: Group 0 for EL3, Secure Group 1 for S-EL1, and non-secure Group 1 for EL1. The CPU interface determines which interrupt to send based on the EL level and security status. However, FIQ does not represent a secure interrupt and is used differently depending on the group and CPU state. Peripherals can support secure interrupts as SGI, PPI, or SPI, with LPI only supporting non-secure interrupts.TrustZone 是一种系统级安全解决方案，可以使用支持 TrustZone 和特定功能（如安全地址空间过滤、安全定时器、安全时钟、安全中断、密钥管理、安全 ROM 代码、安全调试和安全 SRAM）的 CPU 在 SoC 芯片中实现。TrustZone 允许轻松管理外围设备，包括访问权限、用于安全和非安全访问的主控制以及安全中断生成和 CPU 响应。本文讨论了如何在 TrustZone 中生成安全中断，涉及安全外设、GIC 和 CPU。虽然 GIC 经常被忽视，但了解 TrustZone 如何支持安全中断对于解决相关问题至关重要。CPU 通过检查安全中断是否被屏蔽并确定处理它们的位置来支持安全中断。中断的处理取决于 EL 级别和异常处理程序。GIC 通过对安全中断进行分组并保护相关 registers 来支持安全中断，允许 CPU 仅在处于安全状态时对其进行配置。在 GICv3 中，使用了三个组：组 0 用于 EL3，安全组 1 用于 S-EL1，非安全组 1 用于 EL1。CPU 接口根据 EL 级别和安全状态确定要发送的中断。但是，FIQ 不代表安全中断，并且根据组和 CPU 状态的不同而有不同的使用方式。外设可以支持 SGI、PPI 或 SPI 等安全中断，而 LPI 仅支持非安全中断。 | |
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| _2024_7_25_14_00_12_ | 2024_7_25 14_00_12 | | | 原文链接失效了?试试备份 | | TAGs:处理器 安全 | | saved date: Thu Jul 25 2024 14:00:12 GMT+0800 (中国标准时间) | |
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| _2024_8_4_16_37_11_ | 2024_8_4 16_37_11 | | Foundation | | 原文链接失效了?试试备份 | | TAGs:处理器 异构计算 | | saved date: Sun Aug 04 2024 16:37:11 GMT+0800 (中国标准时间) | |
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| _2024_8_4_16_46_14_ | 2024_8_4 16_46_14 | | 打破CUDA霸权！ - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 异构计算 | | saved date: Sun Aug 04 2024 16:46:14 GMT+0800 (中国标准时间) | |
| _2025-02-27_11：58：26_ | 2025-02-27 11：58：26 | | DeepSeek开源周总结和感悟【更新至第三天】 - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 异构计算 软硬协同 大模型 | | Summary: This text is a summary of a blog post about DeepSeek, an open-source project that optimizes AI performance on specific hardware. The author expresses their feelings about the challenges of completing such work in foreign AI companies due to hardware restrictions. They highlight three projects, FlashMLA, DeepEP, and DeepGEMM, and their contributions to improving AI performance on limited hardware. The author emphasizes the importance of understanding both AI models and hardware for optimal performance and the potential impact of DeepSeek on the industry.本文是关于 DeepSeek 的博客文章的摘要，DeepSeek 是一个开源项目，可优化特定硬件上的 AI 性能。作者表达了他们对由于硬件限制而在国外 AI 公司完成此类工作所面临的挑战的感受。他们重点介绍了 FlashMLA、DeepEP 和 DeepGEMM 三个项目，以及它们对在有限硬件上提高 AI 性能的贡献。作者强调了了解 AI 模型和硬件以实现最佳性能的重要性，以及 DeepSeek 对行业的潜在影响。 | |
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| _2025-05-18_14：09：58_ | 2025-05-18 14：09：58 | | SoC 越复杂，NoC 越关键！ | | 原文链接失效了?试试备份 | | TAGs:处理器 总线 | | Summary: The complexity of System-on-Chips (SoC) is increasing exponentially, making Network-on-Chips (NoC) increasingly crucial for efficient and scalable data transfer and communication within the chip. As AI, high-performance computing (HPC), and other data-intensive applications continue to evolve, advanced NoC solutions are required to address the challenges of large-scale SoC design. Despite the opportunities brought by these technological advancements, there are significant challenges for SoC designers, including rapidly expanding architectures, tight deadlines, scarce professional talent, low resource utilization, and fragmented design toolchains. The text discusses the growing complexity of SoCs, the importance of NoCs, and the challenges faced by SoC designers in the era of big chiplets.片上系统 （SoC） 的复杂性呈指数级增长，这使得片上网络 （NoC） 对于芯片内高效且可扩展的数据传输和通信越来越重要。随着 AI、高性能计算 （HPC） 和其他数据密集型应用的不断发展，需要先进的 NoC 解决方案来应对大规模 SoC 设计的挑战。尽管这些技术进步带来了机遇，但 SoC 设计人员面临着重大挑战，包括快速扩展的架构、紧迫的期限、稀缺的专业人才、低资源利用率和碎片化的设计工具链。本文讨论了 SoC 日益增长的复杂性、NoC 的重要性以及 SoC 设计人员在小芯片时代面临的挑战。 | |
| _2025-04-08_18：05：19_ | 2025-04-08 18：05：19 | | - | | 原文链接失效了?试试备份 | | TAGs:处理器 | | Summary: A user named Romer shares their experience of designing a four-core processor after being inspired by a course on computer architecture. They started by deciding on cache sizes, network FIFO sizes, and branch predictor parameters using the gem5 simulator. They chose a directory consistency protocol for the cache coherence protocol and improved upon a protocol from a Carnegie Mellon University course. They then designed each module's specific implementation and began coding. However, they encountered issues when integrating the entire system. Despite pausing the project to focus on school, they were eventually offered a project opportunity and continued their studies in computer architecture. They also learned about the importance of understanding operating systems for processor design.一位名叫 Romer 的用户分享了他们在受到计算机体系结构课程的启发后设计四核处理器的经验。他们首先使用 gem5 模拟器确定缓存大小、网络 FIFO 大小和分支预测器参数。他们为缓存一致性协议选择了目录一致性协议，并在卡内基梅隆大学课程中的协议进行了改进。然后，他们设计了每个模块的特定实现并开始编码。但是，他们在集成整个系统时遇到了问题。尽管暂停了项目以专注于学校，但他们最终获得了一个项目机会并继续学习计算机体系结构。他们还了解了了解作系统对处理器设计的重要性。 | |
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| _2025-04-03_17：31：37_ | 2025-04-03 17：31：37 | | 环形振荡器与CPU硬件随机数解析- DeepSeek - 探索未至之境 | | 原文链接失效了?试试备份 | | TAGs:处理器 | | Summary: The input discusses the relationship between ring oscillators and CPU hardware random number generation. A ring oscillator is a circuit made up of an odd number of flip-flops connected in a loop, which generates oscillations with a frequency dependent on the number of flip-flops and their delays. It's simple in structure but can be less stable due to environmental factors. CPU hardware random number generators typically rely on physical phenomena for randomness, such as electronic noise or clock jitter. Ring oscillators can be used as a source of this randomness due to the unpredictable delay variations in each flip-flop, which can be collected to generate random numbers. However, the user may be interested in how ring oscillators are integrated into CPUs as hardware random number generators. Possible methods include Intel's RdRand instruction, but the specifics are unclear. Research is needed to confirm common implementation techniques. Additionally, hardware random number generators often require post-processing, such as using hash or encryption algorithms to ensure uniform distribution and eliminate bias. The input also discusses the advantages and disadvantages of ring oscillator-based methods compared to other random number generation techniques, such as those based on avalanche diodes or quantum effects. Ring oscillators provide a low-cost, easily integratable randomness source but may require more calibration and post-processing. They also need to meet security requirements, such as resistance to attacks and unpredictability. The input is intended for computer science or electronics engineering students or developers interested in hardware security. The explanation should cover both theoretical principles and practical applications, providing examples of CPU implementations, such as Intel or AMD processors. The explanation should be clear, logical, and structured, starting with ring oscillators, then discussing hardware random number generators, and finally discussing their advantages, disadvantages, and applications. Technical details, such as the number of flip-flops or the method of quantifying the entropy source, should also be checked for accuracy. Ring oscillators and CPU hardware random number generators are closely related concepts in computer hardware design. The following is a detailed analysis of both concepts and their relationship. | |
| _2025-05-28_12：05：24_ | 2025-05-28 12：05：24 | | 打破国外厂商垄断，这几家车规电机驱动芯片厂商开始实现替代-电子工程专辑 | | 原文链接失效了?试试备份 | | TAGs:处理器 车 | | Summary: This text is about the development and competition in the market for car rule electric motor drive chips, which are essential components for electric vehicles. The text discusses how China's domestic companies are starting to challenge the dominance of foreign companies in this field, with companies like PeakPlus Technology, Mustek, and BYD Semiconductor emerging as significant players. The text also mentions the importance of these chips in electric vehicles, as they determine key performance indicators such as hill-climbing ability, acceleration, and maximum speed. The text concludes by mentioning the future direction of car rule electric motor drive chips, including the use of self-developed cores, algorithm hardwareization, and high integration.本文是关于 car rule 电动机驱动芯片市场的发展和竞争，这些芯片是电动汽车的重要组成部分。本文讨论了中国国内公司如何开始挑战外国公司在该领域的主导地位，PeakPlus Technology、Mustek 和 BYD Semiconductor 等公司成为重要参与者。文中还提到了这些芯片在电动汽车中的重要性，因为它们决定了爬坡能力、加速度和最大速度等关键性能指标。文最后提到了 Car Rule 电机驱动芯片的未来方向，包括使用自研内核、算法硬件化、高集成度。 | |
| _2024_8_29_18_02_17_ | 2024_8_29 18_02_17 | | 这一次，轮到云计算定义芯片了 | | 原文链接失效了?试试备份 | | TAGs:处理器 | | saved date: Thu Aug 29 2024 18:02:17 GMT+0800 (中国标准时间) | |
| _2025-05-15_11：21：02_ | 2025-05-15 11：21：02 | | 文献翻译_Design of True Random Number Generator Based on Multi-stage Feedback Ring Oscillator 基于多级反馈环形振荡器的真随机数发生器设计 | | 原文链接失效了?试试备份 | | TAGs:处理器 随机数 | | Summary: A new method for generating true random numbers on FPGAs using a multi-level feedback ring oscillator (MSFRO) as the entropy source is proposed in this article. By adding a multi-level feedback structure to traditional ring oscillators, the clock jitter range is expanded, increasing the clock sampling frequency and entropy source randomness. Unlike traditional clock sampling structures, the clock jitter signal generated by MSFRO is used to sample the clock signal from the FPGA's phase-locked loop (PLL). The output values are then XORed to reduce bias and improve randomness. This TRNG was implemented on an Xilinx Virtex-6 FPGA, with low hardware resource consumption and high throughput. Comparisons of entropy sources, hardware resources, and throughput with existing TRNGs showed that the proposed design uses only 24 LUTs and 2 DFFs. Compared to other TRNGs, this design has very low hardware resource usage and achieves a throughput of 290 Mbps. The generated random bit sequence passed NIST SP800-22 and NIST SP80090B tests.本文提出了一种使用多级反馈环形振荡器 （MSFRO） 作为熵源在 FPGA 上生成真随机数的新方法。通过在传统环形振荡器上增加多级反馈结构，扩大了时钟抖动范围，提高了时钟采样频率和熵源随机性。与传统的 clock sampling 结构不同，MSFRO 生成的 clock jitter 信号用于从 FPGA 的锁相环 （PLL） 对 clock 信号进行采样。然后对输出值进行 XOR 运算以减少偏差并提高随机性。该 TRNG 在 Xilinx Virtex-6 FPGA 上实现，具有低硬件资源消耗和高吞吐量。将熵源、硬件资源和吞吐量与现有 TRNG 进行比较表明，所提出的设计仅使用 24 个 LUT 和 2 个 DFF。与其他 TRNG 相比，该设计的硬件资源使用率非常低，吞吐量为 290 Mbps。生成的随机位序列通过了 NIST SP800-22 和 NIST SP80090B 测试。 | |
| _2025-05-15_11：23：24_ | 2025-05-15 11：23：24 | | 环形振荡器与CPU硬件随机数解析 - DeepSeek - 探索未至之境 | | 原文链接失效了?试试备份 | | TAGs:处理器 随机数 | | Summary: A circular oscillator and a CPU hardware random number generator are closely related concepts in computer hardware design. The following is a detailed explanation and analysis of both: | |
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| _2025-06-08_17：17：15_ | 2025-06-08 17：17：15 | | RISC-V SoCReady SystemVIP - Breker Verification Systems | | 原文链接失效了?试试备份 | | TAGs:处理器 验证 | | Summary: The RISC-V SoCReady SystemVIP is a comprehensive verification solution for RISC-V SoCs from Breker. It includes a test suite for functional and performance operation evaluation, synthesis technologies for increased coverage and corner case detection, and is portable across various execution platforms. The test suite covers various aspects such as memory tests, system coherency, paging/IOMMU, system security, power management, and packet generation. The SystemVIP is built on Breker's Test Suite Synthesis platform for effective bug hunting and scenario modeling.RISC-V SoCReady SystemVIP 是 Breker 为 RISC-V SoC 提供的全面验证解决方案。它包括一个用于功能和性能作评估的测试套件，用于增加覆盖范围和极端情况检测的综合技术，并且可以在各种执行平台上移植。该测试套件涵盖内存测试、系统一致性、分页/IOMMU、系统安全、电源管理和数据包生成等各个方面。SystemVIP 基于 Breker 的 Test Suite Synthesis 平台构建，用于有效的错误搜寻和场景建模。 | |
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| _2025_1_23_15：14：47_ | 2025_1_23 15：14：47 | | | 原文链接失效了?试试备份 | | TAGs:处理器 验证 | | saved date: Thu Jan 23 2025 15:14:47 GMT+0800 (中国标准时间) | |
| _2025_1_23_15：14：41_ | 2025_1_23 15：14：41 | | | 原文链接失效了?试试备份 | | TAGs:处理器 验证 | | saved date: Thu Jan 23 2025 15:14:41 GMT+0800 (中国标准时间) | |
| _2025_1_23_15：44：27_ | 2025_1_23 15：44：27 | | Veripool | | 原文链接失效了?试试备份 | | TAGs:处理器 验证 | | saved date: Thu Jan 23 2025 15:44:27 GMT+0800 (中国标准时间) | |
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| _2025-05-19_19：09：58_ | 2025-05-19 19：09：58 | | 基于硬件仿真加速器的PCIe接口验证方法探究和实现 | | 原文链接失效了?试试备份 | | TAGs:处理器 验证 | | Summary: The Cadence Palladium Z1 hardware simulator can reach a maximum frequency of 4MHz, but it doesn't meet the requirements of the PCIe interface. To address this issue, the Palladium platform offers a solution by using SpeedBridge for rate adaptation on both ends.Cadence Palladium Z1 硬件模拟器可以达到 4MHz 的最大频率，但不符合 PCIe 接口的要求。为了解决这个问题，Palladium 平台提供了一种解决方案，使用 SpeedBridge 在两端进行速率自适应。 | |
| _2025-03-10_17：32：56_ | 2025-03-10 17：32：56 | | 高性能CPU微架构应该具有哪些特性-CSDN博客 | | 原文链接失效了?试试备份 | | TAGs:处理器 | | Summary: This text is about CPU microarchitecture and its impact on performance. It discusses various aspects of CPU design, including instruction sets, microarchitecture, and system architecture. The text also mentions specific CPUs and their features, such as Intel's Core and AMD's Cortex-A9. The author emphasizes the importance of understanding microarchitecture to optimize performance and improve system design. The text also touches upon the concept of microservices and their architecture. Overall, the text provides a comprehensive overview of CPU design and its role in modern computing.本文是关于 CPU 微架构及其对性能的影响的。它讨论了 CPU 设计的各个方面，包括指令集、微架构和系统架构。文本还提到了特定的 CPU 及其功能，例如 Intel 的 Core 和 AMD 的 Cortex-A9。作者强调了了解微架构对于优化性能和改进系统设计的重要性。本文还涉及微服务的概念及其架构。总体而言，该文本全面概述了 CPU 设计及其在现代计算中的作用。 | |
| _2024_8_29_16_32_59_ | 2024_8_29 16_32_59 | | 龙芯开源社区 | | 原文链接失效了?试试备份 | | TAGs:处理器 龙芯 | | saved date: Thu Aug 29 2024 16:32:59 GMT+0800 (中国标准时间) | |