| _2025-05-15_11：21：02_ | 2025-05-15 11：21：02 | | 文献翻译_Design of True Random Number Generator Based on Multi-stage Feedback Ring Oscillator 基于多级反馈环形振荡器的真随机数发生器设计 | | 原文链接失效了?试试备份 | | TAGs:处理器 随机数 | | Summary: A new method for generating true random numbers on FPGAs using a multi-level feedback ring oscillator (MSFRO) as the entropy source is proposed in this article. By adding a multi-level feedback structure to traditional ring oscillators, the clock jitter range is expanded, increasing the clock sampling frequency and entropy source randomness. Unlike traditional clock sampling structures, the clock jitter signal generated by MSFRO is used to sample the clock signal from the FPGA's phase-locked loop (PLL). The output values are then XORed to reduce bias and improve randomness. This TRNG was implemented on an Xilinx Virtex-6 FPGA, with low hardware resource consumption and high throughput. Comparisons of entropy sources, hardware resources, and throughput with existing TRNGs showed that the proposed design uses only 24 LUTs and 2 DFFs. Compared to other TRNGs, this design has very low hardware resource usage and achieves a throughput of 290 Mbps. The generated random bit sequence passed NIST SP800-22 and NIST SP80090B tests.本文提出了一种使用多级反馈环形振荡器 （MSFRO） 作为熵源在 FPGA 上生成真随机数的新方法。通过在传统环形振荡器上增加多级反馈结构，扩大了时钟抖动范围，提高了时钟采样频率和熵源随机性。与传统的 clock sampling 结构不同，MSFRO 生成的 clock jitter 信号用于从 FPGA 的锁相环 （PLL） 对 clock 信号进行采样。然后对输出值进行 XOR 运算以减少偏差并提高随机性。该 TRNG 在 Xilinx Virtex-6 FPGA 上实现，具有低硬件资源消耗和高吞吐量。将熵源、硬件资源和吞吐量与现有 TRNG 进行比较表明，所提出的设计仅使用 24 个 LUT 和 2 个 DFF。与其他 TRNG 相比，该设计的硬件资源使用率非常低，吞吐量为 290 Mbps。生成的随机位序列通过了 NIST SP800-22 和 NIST SP80090B 测试。 | |
| _2025-05-15_11：23：24_ | 2025-05-15 11：23：24 | | 环形振荡器与CPU硬件随机数解析 - DeepSeek - 探索未至之境 | | 原文链接失效了?试试备份 | | TAGs:处理器 随机数 | | Summary: A circular oscillator and a CPU hardware random number generator are closely related concepts in computer hardware design. The following is a detailed explanation and analysis of both: | |
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