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| _2025-04-14_15：51：22_ | 2025-04-14 15：51：22 | | RISC-V架构下外设虚拟化解决方案 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 IO | | Summary: RISC-V architecture introduced IOMMU to address DMA transfer performance issues in virtual machines. IOMMU provides GPA to SPA address translation ability for each DMA device through a device table. With IOMMU, the DMA data transfer process can be automatically handled by the hardware, reducing the need for hypervisor OS to capture every DMA transfer. Additionally, IOMMU allows CPU and DMA to share the same process table, enabling VUs user processes to use DMA directly. For DMA devices with IOVA to GPA remapping, such as GPUs, IOMMU's process table can be used for automatic IOVA to GPA to SPA address translation. RISC-V's IOMMU supports PCIe's ATS and PRI interfaces, allowing for optimized MSI address translation for PCIe devices. (图1 - IOMMU下的两级地址翻译) | |
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| _2025-03-20_16：47：51_ | 2025-03-20 16：47：51 | | RISC-V AIA support for RISC-V machines — QEMU documentation | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: The input describes the implementation of Advanced Interrupt Architecture (AIA) support in the virtRISC-V machine for TCG and KVM accelerators. There are two main modes: "aia=aplic" and "aia=aplic-imsic". The former adds one or more APLIC (Advanced Platform Level Interrupt Controller) devices, while the latter adds one or more APLIC devices and an IMSIC (Incoming MSI Controller) device for each CPU. The user behavior remains the same regardless of the accelerator used, but the emulated components change between userspace and kernel space depending on the accelerator. When running TCG, all controllers are emulated in userspace, while KVM provides no m-mode, resulting in no m-mode APLIC or IMSIC emulation. The table provided outlines how the AIA and accelerator options determine what is emulated in userspace.输入描述了 virtRISC-V 机器中对 TCG 和 KVM 加速器的高级中断架构 （AIA） 支持的实现。有两种主要模式：“aia=aplic”和“aia=aplic-imsic”。前者为每个 CPU 添加一个或多个 APLIC （高级平台级中断控制器） 设备，而后者为每个 CPU 添加一个或多个 APLIC 设备和一个 IMSIC （传入 MSI 控制器） 设备。无论使用何种加速器，用户行为都保持不变，但仿真组件在用户空间和内核空间之间会发生变化，具体取决于加速器。运行 TCG 时，所有控制器都在用户空间中仿真，而 KVM 不提供 m 模式，因此没有 m 模式 APLIC 或 IMSIC 仿真。提供的表格概述了 AIA 和 accelerator 选项如何确定在用户空间中模拟的内容。 | |
| _2025-03-20_16：50：26_ | 2025-03-20 16：50：26 | | RISC-V IOMMU support for RISC-V machines — QEMU documentation | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: This text describes the implementation of RISC-V IOMMU (Input/Output Memory Management Unit) emulation in QEMU (Quick Emulator) version 9.2.90. The emulation includes a PCI reference device (riscv-iommu-pci) and a platform bus device (riscv-iommu-sys) for RISC-V machines. The PCI device can be added to the 'virt' RISC-V machine using the command line option '-device riscv-iommu-pci'. The IOMMU behavior is defined by the spec but its operation is OS dependent, with the current Linux kernel support (linux-v8) not yet fully feature-complete. The IOMMU emulation was tested using the Ventana Micro Systems kernel repository, which includes patches for KVM VFIO passthrough with irqbypass. The riscv-iommu-pci device can be configured with options such as bus, ioatc-limit, intremap, ats, off, s-stage, and g-stage. The riscv-iommu-sys device is implemented as a platform bus device for RISC-V boards and can be enabled using the 'iommu-sys' machine option.本文描述了 QEMU （Quick Emulator） 版本 9.2.90 中 RISC-V IOMMU （输入/输出内存管理单元） 仿真的实现。仿真包括用于 RISC-V 计算机的 PCI 参考设备 （riscv-iommu-pci） 和平台总线设备 （riscv-iommu-sys）。可以使用命令行选项 '-device riscv-iommu-pci' 将 PCI 设备添加到 'virt' RISC-V 机器上。IOMMU 行为由规范定义，但其作取决于作系统，当前的 Linux 内核支持 （linux-v8） 尚未完全完成功能。IOMMU 仿真使用 Ventana Micro Systems 内核存储库进行了测试，其中包括使用 irqbypass 的 KVM VFIO 直通补丁。riscv-iommu-pci 设备可以配置 bus、ioatc-limit、intremap、ats、off、s-stage 和 g-stage 等选项。riscv-iommu-sys 设备是作为 RISC-V 板的平台总线设备实现的，可以使用 'iommu-sys' 机器选项启用。 | |
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| _2025-04-22_14：43：19_ | 2025-04-22 14：43：19 | | RISC-V嵌套虚拟化支持 - 允许Hypervisor上运行Hypervisor_哔哩哔哩_bilibili | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: This page discusses the support for RISC-V nested virtualization, which enables the running of a hypervisor on another hypervisor, referred to as the "nested hypervisor," at the guest level on the first hypervisor. This architecture allows for increased security and efficiency in virtualized systems.本页讨论了对 RISC-V 嵌套虚拟化的支持，它允许在第一个虚拟机管理程序的来宾级别在另一个虚拟机管理程序（称为“嵌套虚拟机管理程序”）上运行虚拟机管理程序。此体系结构可以提高虚拟化系统的安全性和效率。 | |
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| _2025-05-23_15：01：36_ | 2025-05-23 15：01：36 | | [PULL 12_22] riscv_ Allow user to set the satp mode | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 qemu satp | | Summary: This is a series of commit messages from the RISC-V QEMU project. The commits introduce various changes to the RISC-V CPU implementation in QEMU. Some of the changes include: | |
| _2025-05-09_14：46：54_ | 2025-05-09 14：46：54 | | sig-qemu@lists.riscv.org _ RVA23 profile support | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 qemu | | Summary: A group discussion on the RVA23 profile support for QEMU is taking place on the sig-qemu list. The new RVA23 profile, which includes mandatory extensions Ss1p13, Zimop, Zcmop, Supm, Ssnpm, Shgatpa, Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, and Shvsatpa, and optional extensions Zabha, Ziccamoc, Zama16b, Sdex, Ssstrict, Svvptc, and Sspm, is being discussed. The group members are encouraging each other to implement these extensions on QEMU and update the progress on the group.关于 RVA23 配置文件对 QEMU 支持的小组讨论正在 sig-qemu 列表中进行。新的 RVA23 配置文件，包括强制性扩展 Ss1p13、Zimop、Zcmop、Supm、Ssnpm、Shgatpa、Ssstateen、Shcounterenw、Shvstvala、Shtvala、Shvstvecd 和 Shvsatpa，以及可选扩展 Zabha、Ziccamoc、Zama16b、Sdex、Ssstrict、Svvptc 和 Sspm，正在讨论中。小组成员互相鼓励在 QEMU 上实施这些扩展，并更新小组的进展。 | |
| _2025-03-10_15：36：23_ | 2025-03-10 15：36：23 | | riscv kvm 方案代码调研 _ blog | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: This text describes the virtualization of memory, CPU, timer, and interrupts in the context of a virtual machine using KVM (Kernel-based Virtual Machine) for RISC-V processors. The memory virtualization includes the conversion from Guest Physical Address (GPA) to Host Physical Address (HVA), with sub-steps for data structures and process analysis. The CPU virtualization involves the VCPU execution flow, including KVM_VCPU_RUN, vCPU scheduling, and hs timer tick details. The timer virtualization includes RISC-V timer support, user-level access, guest access with guest timer tick processing and guest time, and sstc vstimecmp. Interrupt virtualization includes PIC interrupt injection with registration and triggering processes, and AIA imsic interrupt processing with kvm_riscv_vcpu_aia_update, guest access to siselect and sireg, MMIO injection, and imsic doorbell interrupt.本文描述了使用 KISC-V 处理器的 KVM（基于内核的虚拟机）在虚拟机环境中对内存、CPU、定时器和中断进行虚拟化。内存虚拟化包括从来宾物理地址 （GPA） 到主机物理地址 （HVA） 的转换，以及用于数据结构和进程分析的子步骤。CPU 虚拟化涉及 VCPU 执行流程，包括 KVM_VCPU_RUN、vCPU 调度和 hs 计时器 tick 详细信息。计时器虚拟化包括 RISC-V 计时器支持、用户级访问、使用来宾计时器时钟周期处理和来宾时间的来宾访问以及 sstc vstimecmp。中断虚拟化包括带有注册和触发进程的 PIC 中断注入、带有 kvm_riscv_vcpu_aia_update 的 AIA imsic 中断处理、来宾对 siselect 和 sireg 的访问、MMIO 注入和 imsic 门铃中断。 | |
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| _2025-04-11_14：07：01_ | 2025-04-11 14：07：01 | | riscv_ KVM_ Remove unnecessary vcpu kick - kernel_git_riscv_linux.git - RISC-V Linux kernel tree | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: The RISC-V Linux kernel tree had a commit on February 21, 2025, by Bill Xiang, which removed an unnecessary vCPU kick after writing to the vs\_file in kvm\_riscv\_vcpu\_aia\_imsic\_inject. This change is applicable for vCPUs that are running and have their interrupts forwarded directly as an MSI. For vCPUs that are descheduled after emulating WFI, the guest external interrupt is enabled, causing the writing to the vs\_file to cause a guest external interrupt and wake up the vCPU in hgei\_interrupt to handle the interrupt properly. The commit was reviewed by Andrew Jones and Radim Krčmář and signed off by Anup Patel. The diff shows one deletion in arch/riscv/kvm/aia\_imsic.c.RISC-V Linux 内核树于 2025 年 2 月 21 日由 Bill Xiang 提交，该提交在写入 kvm\_riscv\_vcpu\_aia\_imsic\_inject 中的 vs\_file 后删除了不必要的 vCPU 踢出。此更改适用于正在运行且其中断作为 MSI 直接转发的 vCPU。对于在模拟 WFI 后取消调度的 vCPU，将启用客户机外部中断，从而导致对 vs\_file 的写入导致客户机外部中断，并唤醒 hgei\_interrupt 中的 vCPU 以正确处理中断。该提交由 Andrew Jones 和 Radim Krčmář 审查，并由 Anup Patel 签署。差异显示 arch/riscv/kvm/aia\_imsic.c 中的一个删除。 | |
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| _2025-04-03_10：20：36_ | 2025-04-03 10：20：36 | | 中国科学院软件研究所团队推动 Cloud Hypervisor 官方支持 RISC-V | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 | | Summary: The Chinese Academy of Sciences Software Research Institute team has officially released Cloud-Hypervisor v45.0, which adds experimental RISC-V support. This makes Cloud-Hypervisor the first lightweight virtualization solution to integrate with Kata-containers and fully support RISC-V. The update received attention in the overseas open-source community, with Phoronix reporting on its significance as the first step for RISC-V in the server virtualization domain. Cloud-Hypervisor, built using the Rust programming language, aims to create a complete Rust virtualization software ecosystem for future RISC-V chips. As the bridge connecting the KVM virtualization engine with upper-layer applications, Cloud-Hypervisor is a crucial implementation in the RISC-V virtualization software landscape. It provides a runtime environment for Kubernetes and other container orchestration systems with virtual machine-level isolation, enhancing security while implementing flat fault/performance isolation within clusters. Cloud-Hypervisor, a modern, lightweight, and cross-platform virtualization monitoring program, has been developed over five years and has contributed significantly to the RISC-V community, ranking ninth in total contributions and first in RISC-V contributions globally. To achieve Cloud Hypervisor's RISC-V support, the team focused on three core areas: 1) virtualization core capabilities, 2) engineering system upgrades, and 3) production-level stability assurance. These efforts have led to the initial support of hypervisor, arch, vm-allocator, devices, and vmm modules on the RISC-V architecture. The team plans to further enhance Cloud-Hypervisor's RISC-V architecture support by addressing the feature differences between RISC-V, x86, and ARM, completing FDT generation links, adding UEFI boot support, and supporting PMU, IOMMU, and TPM devices. OpenEuler, as the first verification platform for RISC-V virtualization capabilities, will continue to support Cloud-Hypervisor on the openEuler platform and integrate it with the Kata Containers secure container technology path, creating a secure container infrastructure based on openEuler RISC-V. The release of Cloud-Hypervisor v45.0 marks a significant milestone in the RISC-V virtualization roadmap. By implementing systemic breakthroughs in instruction register operations, AIA interrupt controller integration, and memory management, the team is building a virtualization ability matrix that conforms to the RVA23 specification. This achievement not only provides a verified RISC-V virtualization implementation baseline for the open-source community but also lays the foundation for the standardized evolution of future RISC-V virtualization-related software, enabling RISC-V server ecosystems to possess software validation capabilities from chip features to container runtimes even before the hardware platform matures.中国科学院软件研究院团队正式发布 Cloud-Hypervisor v45.0，增加了实验性的 RISC-V 支持。这使得 Cloud-Hypervisor 成为第一个与 Kata 容器集成并完全支持 RISC-V 的轻量级虚拟化解决方案。该更新受到了海外开源社区的关注，Phoronix 报告了其作为 RISC-V 在服务器虚拟化领域的第一步的重要性。Cloud-Hypervisor 使用 Rust 编程语言构建，旨在为未来的 RISC-V 芯片创建一个完整的 Rust 虚拟化软件生态系统。作为连接 KVM 虚拟化引擎与上层应用程序的桥梁，Cloud-Hypervisor 是 RISC-V 虚拟化软件领域中的关键实现。它为 Kubernetes 和其他容器编排系统提供了一个具有虚拟机级隔离的运行时环境，在增强安全性的同时在集群内实施平面故障/性能隔离。Cloud-Hypervisor 是一个现代、轻量级和跨平台的虚拟化监控程序，已经开发了五年多，为 RISC-V 社区做出了重大贡献，在全球总贡献中排名第九，在 RISC-V 贡献中排名第一。为了实现 Cloud Hypervisor 的 RISC-V 支持，该团队专注于三个核心领域：1） 虚拟化核心能力，2） 工程系统升级，以及 3） 生产级稳定性保证。这些努力导致了对 RISC-V 架构上的 hypervisor、arch、vm-allocator、devices 和 vmm 模块的初步支持。 该团队计划通过解决 RISC-V、x86 和 ARM 之间的功能差异，完成 FDT 生成链接，添加 UEFI 启动支持，并支持 PMU、IOMMU 和 TPM 设备，进一步增强 Cloud-Hypervisor 的 RISC-V 架构支持。OpenEuler 作为首个 RISC-V 虚拟化能力的验证平台，将继续在 openEuler 平台上支持 Cloud-Hypervisor，并与 Kata Containers 安全容器技术路径集成，打造基于 openEuler RISC-V 的安全容器基础设施。Cloud-Hypervisor v45.0 的发布标志着 RISC-V 虚拟化路线图中的一个重要里程碑。通过在指令寄存器作、AIA 中断控制器集成和内存管理方面实现系统性突破，该团队正在构建符合 RVA23 规范的虚拟化能力矩阵。这一成果不仅为开源社区提供了经过验证的 RISC-V 虚拟化实现基线，也为未来 RISC-V 虚拟化相关软件的标准化演进奠定了基础，使 RISC-V 服务器生态系统在硬件平台成熟之前就拥有从芯片特性到容器运行时的软件验证能力。 | |
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| _2025-03-27_11：31：09_ | 2025-03-27 11：31：09 | | riscv_ KVM_ Remove unnecessary vcpu kick - kernel_git_riscv_linux.git - RISC-V Linux kernel tree | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 中断 | | Summary: The RISC-V Linux kernel tree had a commit on February 21, 2025, by Bill Xiang, which removed an unnecessary vCPU kick after writing to the vs\_file in kvm\_riscv\_vcpu\_aia\_imsic\_inject. This change is applicable for vCPUs that are running and have their interrupts forwarded directly as an MSI. For vCPUs that are descheduled after emulating WFI, the guest external interrupt is enabled, causing the writing to the vs\_file to cause a guest external interrupt and wake up the vCPU in hgei\_interrupt to handle the interrupt properly. The commit was reviewed by Andrew Jones and Radim Krčmář and signed off by Anup Patel. The diff shows one deletion in arch/riscv/kvm/aia\_imsic.c.RISC-V Linux 内核树于 2025 年 2 月 21 日由 Bill Xiang 提交，该提交在写入 kvm\_riscv\_vcpu\_aia\_imsic\_inject 中的 vs\_file 后删除了不必要的 vCPU 踢出。此更改适用于正在运行且其中断作为 MSI 直接转发的 vCPU。对于在模拟 WFI 后取消调度的 vCPU，将启用客户机外部中断，从而导致对 vs\_file 的写入导致客户机外部中断，并唤醒 hgei\_interrupt 中的 vCPU 以正确处理中断。该提交由 Andrew Jones 和 Radim Krčmář 审查，并由 Anup Patel 签署。差异显示 arch/riscv/kvm/aia\_imsic.c 中的一个删除。 | |
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| _2025-05-14_10：39：52_ | 2025-05-14 10：39：52 | | riscv_ KVM_ Remove unnecessary vcpu kick · torvalds_linux@d252435 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v 虚拟化 中断 | | Summary: A GitHub page displays information about a commit in the Linux kernel project. The commit, made by Bill Xiang, removes an unnecessary vCPU kick in the riscv: KVM (Kernel-based Virtual Machine) code. The vCPU kick is no longer needed when writing to the vs\_file directly forwards an interrupt as an MSI to the vCPU. The commit also modifies the handling of guest external interrupts. The changes were reviewed by Andrew Jones and Radim Krčmář.GitHub 页面显示有关 Linux 内核项目中提交的信息。由 Bill Xiang 提交的提交删除了 riscv： KVM（基于内核的虚拟机）代码中不必要的 vCPU 踢出。写入 vs\_file 将中断作为 MSI 直接转发到 vCPU 时，不再需要 vCPU 踢出。该提交还修改了客户机外部中断的处理。Andrew Jones 和 Radim Krčmář 审查了这些更改。 | |
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