_2024_11_13_11_18_18_2024_11_13 11_18_18
RISC-V timer 在 Linux 中的实现 - 泰晓科技
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TAGs:处理器 risc-v timer
saved date: Wed Nov 13 2024 11:18:18 GMT+0800 (中国标准时间)
_2025_1_26_14:57:41_2025_1_26 14:57:41
Re: [PATCH v7 0_4] Add Sstc extension support - Anup Patel
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TAGs:处理器 risc-v timer SSTC
saved date: Sun Jan 26 2025 14:57:41 GMT+0800 (中国标准时间)
_2025-03-30_14:11:55_2025-03-30 14:11:55
RISC-V SSTC扩展对Linux CRNG影响分析 - DeepSeek - 探索未至之境
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TAGs:处理器 risc-v timer SSTC random
Summary: The user is asking for an analysis of the impact of RISC-V's SSTC extension on Linux's CRNG (Cryptographic Random Number Generator) and the getrandom system call. The SSTC extension may refer to "Supervisor Software Time Compare" or some time-related extension, but it's not clear without checking the search results. However, the user's question seems to involve RISC-V's security vulnerabilities or random number generation mechanisms. For instance, one page mentions that RISC-V enabled the general CPU vulnerability reporting feature in Linux 6.12 kernel, including the detection and mitigation status. This might be related to system security, which in turn affects the reliability of the random number generator. CRNG is a random number generation module in the Linux kernel, while getrandom is a system call for obtaining random numbers in user space. If RISC-V's SSTC extension introduces new instructions or hardware features, it may affect the efficiency or security of random number generation. For example, one page discusses RISC-V Linux entry address memory optimization, which might involve kernel startup time memory management but is not directly related to random number generation. Another page mentions RISC-V processor vulnerabilities, such as GhostWrite, which can impact system security and, consequently, CRNG's data source. If SSTC extension improves time stamping or counters, it may provide higher-quality interrupt sources or entropy sources for CRNG, thereby improving random number generation speed and quality. One page discusses RISC-V's development in the software ecosystem, including toolchain and compiler optimization, which may indirectly affect the implementation of random number generation in the kernel. For instance, new extensions may require kernel module adaptation and optimization of the entropy collection process. Additionally, pages 7 and 8 discuss RISC-V's integration with the open-source community, which might involve kernel developers supporting RISC-V's new features. If SSTC extension requires kernel-level modifications, such as in driver or architecture-related code, this may impact CRNG's implementation. In summary, while the search results do not directly mention SSTC extension, it can be inferred that SSTC may be a security or time-related extension, and its impact may include improving entropy source collection efficiency, enhancing random number generation security, or requiring kernel adaptation. For example, if SSTC provides hardware random number generation instructions, the kernel's CRNG may utilize these instructions to improve performance and reduce reliance on software entropy sources. Furthermore, vulnerability patches, such as the one mentioned in page 2, can strengthen CRNG's security by addressing hardware vulnerabilities that could lead to random number prediction risks. RISC-V's SSTC (Supervisor Software Time Compare) extension is a part of RISC-V's privileged architecture, primarily used for optimizing time management and interrupt handling. Its impact on Linux's CRNG and getrandom can be summarized as follows:
_2024_11_13_10_23_27_2024_11_13 10_23_27
[PATCH v3 0_4] Add Sstc extension support - Atish Patra
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TAGs:处理器 risc-v timer
saved date: Wed Nov 13 2024 10:23:27 GMT+0800 (中国标准时间)
_2024_11_14_12_01_18_2024_11_14 12_01_18
[v3,4_4] RISC-V_ KVM_ Support sstc extension - Patchwork
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TAGs:处理器 risc-v timer
saved date: Thu Nov 14 2024 12:01:18 GMT+0800 (中国标准时间)
_2025_1_26_15:55:23_2025_1_26 15:55:23
riscv kvm timer bug 问题分析 | blog
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TAGs:处理器 risc-v timer
saved date: Sun Jan 26 2025 15:55:23 GMT+0800 (中国标准时间)