| _2025-06-13_15：48：51_ | 2025-06-13 15：48：51 | | 解析RISCV fence指令 - RISC-V - 进迭RISC-V论坛 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA FENCE | | Summary: This text discusses the use of fence instructions in the RISC-V instruction set to ensure ordered memory access for specific software scenarios. Fence instructions ensure that operations before the fence occur before those after it, preventing unpredictable results. The text provides an example of how fence instructions are used to ensure the order of store and load operations for two cores. It also explains the different formats and uses of fence instructions, including fence.i for ensuring ordered memory access for instruction fetch.本文讨论了在 RISC-V 指令集中使用 fence 指令来确保特定软件场景的有序内存访问。围栏指令可确保围栏之前的作先于围栏之后的作发生，从而防止出现不可预知的结果。该文本提供了一个示例，说明如何使用 fence 指令来确保两个内核的 store 和 load 作的顺序。它还解释了 fence 指令的不同格式和用法，包括 fence.i 以确保指令获取的有序内存访问。 | |
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| _2025-02-28_14：00：26_ | 2025-02-28 14：00：26 | | tech-attached-matrix-extension@lists.riscv.org _RISC-V AME 扩展的 SiFive 提案 --- tech-attached-matrix-extension@lists.riscv.org _ | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA Matrix | | Summary: This text is a discussion between team members regarding the Zvma Attached Matrix Extension (AME) proposal. They find the specification clear and elegant, offering significant matrix computation bandwidth while maintaining software-friendliness. However, they have some concerns about physical design friendliness, specifically the placement of matrix computation logic alongside RAM/flop states and the potential routing contention between the computation block and on-chip memory. They suggest making the data layout microarchitecture (uarch) defined instead of locked at the ISA level and allowing alternative punning schemes in future extensions for greater flexibility. They also recommend specifying that matrix data should be marked as "unspecified" following any matrix configuration change. The team is considering the uarch based on the proposal and looks forward to continued collaboration as Zvma progresses toward ratification.本文是团队成员之间关于 Zvma 附加矩阵扩展 （AME） 提案的讨论。他们发现规范清晰而优雅，在保持软件友好性的同时提供了大量的矩阵计算带宽。然而，他们对物理设计友好性有一些担忧，特别是矩阵计算逻辑与 RAM/flop 状态一起放置，以及计算块和片上存储器之间潜在的路由争用。他们建议在 ISA 级别定义而不是锁定数据布局微架构 （uarch），并在未来的扩展中允许使用其他双关模式以获得更大的灵活性。他们还建议指定在矩阵配置更改后应将矩阵数据标记为“未指定”。该团队正在根据该提案考虑 uarch，并期待在 Zvma 获得批准的过程中继续合作。 | |
| _2025-02-28_14：05：35_ | 2025-02-28 14：05：35 | | tech-attached-matrix-extension@lists.riscv.org _RISC-V AME 扩展的 SiFive 提案 --- tech-attached-matrix-extension@lists.riscv.org _ | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA Matrix | | Summary: The text discusses a feedback exchange between team members regarding the Zvma Attached Matrix Extension (AME) proposal. The team, T1, has reviewed the proposal and finds it clear and elegant, offering significant matrix computation bandwidth while maintaining software-friendliness. They suggest some improvements, including making the data layout microarchitecture (uarch) defined instead of locked at the ISA level, addressing consistency challenges in multi-core scenarios, and specifying that matrix data should be marked as "unspecified" following any matrix configuration change. They also discuss concerns about physical design friendliness, specifically the placement of matrix computation logic alongside RAM/flop states and the potential routing contention between the computation block and on-chip memory. They emphasize the importance of addressing these issues to ensure high-performance computation and alignment across different uarch designs.本文讨论了团队成员之间关于 Zvma 附加矩阵扩展 （AME） 提案的反馈交流。T1 团队审查了该提案，发现它清晰而优雅，在保持软件友好性的同时提供了大量的矩阵计算带宽。他们提出了一些改进建议，包括在 ISA 级别定义而不是锁定数据布局微架构 （uarch），解决多核场景中的一致性挑战，以及指定在任何矩阵配置更改后应将矩阵数据标记为 “unspecified”。他们还讨论了对物理设计友好性的担忧，特别是矩阵计算逻辑与 RAM/flop 状态一起放置，以及计算块和片上存储器之间潜在的布线争用。他们强调了解决这些问题的重要性，以确保不同 uarch 设计之间的高性能计算和对齐。 | |
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| _2025-04-11_11：28：55_ | 2025-04-11 11：28：55 | | RISC-V 密码学指令扩展（K扩展）功能概述 - WuSiYu Blog | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: This blog post is about RISC-V's cryptographic extension (K extension) for IT-related experiments. The K extension provides a series of cryptography-related instructions, which are similar to other instructions in terms of using general registers and maintaining the principle of two reads and one write. Compared to software implementation, using these instructions can enhance the speed of cryptographic algorithms and reduce the size of applications. | |
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| _2025-04-18_19：26：06_ | 2025-04-18 19：26：06 | | The RISC-V Instruction Set Manual_ Volume II_ Privileged Architecture | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: This document describes the RISC-V privileged architecture, which covers aspects of RISC-V systems beyond the unprivileged ISA. It includes privileged instructions and additional functionality required for running operating systems and attaching external devices. The document includes the terminology used for different software stack components, the concept of privilege levels, and the use of control and status registers (CSRs). The RISC-V architecture supports three privilege levels: Machine, Supervisor, and User. The Machine level has the highest privileges and is the only mandatory privilege level for a RISC-V hardware platform. The Supervisor level is used for operating systems and other privileged software, while the User level is used for applications. The document also discusses debug mode and control and status registers (CSRs), including their address mapping conventions and a CSR listing. The CSR address space is divided into unprivileged and user-level CSRs, supervisor-level CSRs, hypervisor and virtual supervisor CSRs, and machine-level CSRs. The document also mentions the Zicsr extension, which is required for all RISC-V implementations, and the SYSTEM major opcode used for all privileged instructions.本文档介绍了 RISC-V 特权体系结构，它涵盖了非特权 ISA 之外的 RISC-V 系统的各个方面。它包括运行作系统和连接外部设备所需的特权指令和附加功能。本文档包括用于不同软件堆栈组件的术语、权限级别的概念以及控制和状态寄存器 （CSR） 的使用。RISC-V 架构支持三个权限级别：Machine、Supervisor 和 User。Machine 级别具有最高权限，并且是 RISC-V 硬件平台的唯一强制权限级别。Supervisor 级别用于作系统和其他特权软件，而 User 级别用于应用程序。本文档还讨论了调试模式以及控制和状态寄存器 （CSR），包括它们的地址映射约定和 CSR 列表。CSR 地址空间分为非特权和用户级 CSR、主管级 CSR、虚拟机管理程序和虚拟主管 CSR 以及计算机级 CSR。该文档还提到了 Zicsr 扩展，这是所有 RISC-V 实现所必需的，以及用于所有特权指令的 SYSTEM 主要作码。 | |
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| _2025-05-23_16：12：49_ | 2025-05-23 16：12：49 | | 进迭时空RISC-V Vector技术实践 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA Vector | | Summary: This text discusses the benefits of RISC-V Vector, a more flexible programming model compared to traditional SIMD instructions, in improving the decoupling between software and hardware. RISC-V Vector supports single instruction multiple data parallel processing while providing higher-level abstractions for developers. The text uses RISC-V Vector 1.0 as an example, explaining how it allows a single program to run on hardware with different vector register widths, and how the element mask function handles excess elements without requiring special handling like in SIMD instructions. The text also mentions that the first-generation RISC-V CPUs, X60 and A60, support RISC-V Vector 1.0 and provide significant performance improvements in various tests compared to Cortex-A55's SIMD instructions.本文讨论了 RISC-V Vector（与传统 SIMD 指令相比，RISC-V Vector）是一种更灵活的编程模型，在改善软件和硬件之间的解耦方面的优势。RISC-V Vector 支持单指令多数据并行处理，同时为开发人员提供更高级别的抽象。本文以 RISC-V Vector 1.0 为例，解释了它如何允许单个程序在具有不同矢量寄存器宽度的硬件上运行，以及元素掩码函数如何处理多余的元素，而无需像 SIMD 指令那样进行特殊处理。文中还提到，第一代 RISC-V CPU X60 和 A60 支持 RISC-V Vector 1.0，与 Cortex-A55 的 SIMD 指令相比，在各种测试中提供了显著的性能改进。 | |
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| _2025-03-25_14：43：07_ | 2025-03-25 14：43：07 | | riscv-profiles_src_rvb23-profile.adoc at main · riscv_riscv-profiles | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: The provided text is a GitHub page about the RVB23 profile for RISC-V application processors. It outlines the mandatory and optional ISA features available to user-mode (RVB23U64) and supervisor-mode (RVB23S64) execution environments in 64-bit RVB applications processors. The page also mentions various extensions and options, some of which are localized, development, expansion, or transitory. The RVB23 profile is a customizable 64-bit application processor profile that provides a large set of features but allows optionality for more expensive and targeted extensions.提供的文本是有关 RISC-V 应用程序处理器的 RVB23 配置文件的 GitHub 页面。它概述了 64 位 RVB 应用处理器中的用户模式 （RVB23U64） 和监控器 模式 （RVB23S64） 执行环境可用的强制性和可选 ISA 功能。该页面还提到了各种扩展和选项，其中一些是本地化的、开发的、扩展的或临时的。RVB23 配置文件是一种可定制的 64 位应用处理器配置文件，它提供大量功能，但允许选择更昂贵和有针对性的扩展。 | |
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| _2025-02-26_11：29：14_ | 2025-02-26 11：29：14 | | tech-announce@lists.riscv.org _ Public review for Smctr_Ssctr ISA extensions | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: The RISC-V Foundation has initiated a public review period for the proposed Control Transfer Records (Smctr/Ssctr) standard extensions to the RISC-V Instruction Set Architecture (ISA). The review period, which runs from July 23 to August 22, 2024, invites feedback via email or GitHub. The extensions, described in the PDF specification available at github.com, aim to correct and incorporate minor changes during the review process. The Privileged ISA Committee will recommend approval and ratification upon completion of the review. (by Mozilla Orbit AI) | |
| _2025-03-24_10：26：06_ | 2025-03-24 10：26：06 | | wfi __ RISC-V Specification for generic_rv64 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: This page describes the behavior of the wfi (Wait For Interrupt) instruction in the RV64 generic architecture. The instruction causes the processor to enter a low-power state and wait for an interrupt. The behavior of wfi is influenced by the mstatus and hstatus registers. In certain modes and conditions, wfi may cause a trap leading to an Illegal Instruction or Virtual Instruction exception.本页介绍 RV64 通用体系结构中 wfi （等待中断） 指令的行为。该指令使处理器进入低功耗状态并等待中断。wfi 的行为受 mstatus 和 hstatus 寄存器的影响。在某些模式和条件下，wfi 可能会导致导致非法指令或虚拟指令异常的陷阱。 | |
| _2025-03-25_10：58：25_ | 2025-03-25 10：58：25 | | [1_5] RISC-V_ KVM_ Forward SEED CSR access to user space - Patchwork | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA zkr | | Summary: This text appears to be an email message containing a patch series for the RISC-V KVM (Kernel-based Virtual Machine) project. The patch series is related to forwarding SEED CSR (Control and Status Register) access to user space when the Zkr extension is available to the guest/VM. The patch includes changes to the `arch/riscv/kvm/vcpu_insn.c` file and is signed off by Anup Patel and reviewed by Andrew Jones. The patch series also includes metadata such as the list ID, mailman version, and sender information.此文本似乎是一封电子邮件，其中包含 RISC-V KVM（基于内核的虚拟机）项目的补丁系列。此补丁系列与当 Zkr 扩展可供来宾/VM 使用时将 SEED CSR（控制和状态寄存器）访问转发到用户空间有关。此补丁包括对 'arch/riscv/kvm/vcpu_insn.c' 文件的更改，由 Anup Patel 签署并由 Andrew Jones 审阅。修补程序系列还包括元数据，例如列表 ID、mailman 版本和发件人信息。 | |
| _2025-03-25_10：58：17_ | 2025-03-25 10：58：17 | | [PULL,02_28] target_riscv_kvm_ Fix exposure of Zkr - Patchwork | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA zkr | | Summary: This text is a diff output showing changes made to the RISC-V QEMU emulator code. The changes include adding a new function `riscv_new_csr_seed()` to create a new value for the SEED CSR, and updating the `rmw_seed()` function to use this new function instead of generating a random value directly. The changes also include adding a new case `KVM_EXIT_RISCV_CSR` to the `kvm_arch_handle_exit()` function to handle the CSR EXIT reason.此文本是一个差异输出，显示了对 RISC-V QEMU 仿真器代码所做的更改。这些更改包括添加新函数 'riscv_new_csr_seed（）' 为 SEED CSR 创建新值，以及更新 'rmw_seed（）' 函数以使用此新函数，而不是直接生成随机值。这些更改还包括向 'kvm_arch_handle_exit（）' 函数添加新的 case 'KVM_EXIT_RISCV_CSR' 来处理 CSR EXIT 原因。 | |
| _2025-04-10_15：22：41_ | 2025-04-10 15：22：41 | | tech-privileged@lists.riscv.org _ [RISC-V] [tech-crypto-ext] Read the seed CSR | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA zkr | | Summary: This discussion revolves around the behavior of the seed CSR (Control and Status Register) in a cryptographic system. The seed CSR is designed to ensure that secret entropy words are not made available multiple times for security reasons. When reading the seed CSR, the system clears (wipes) the entropy contents and changes the state to WAIT, unless there is entropy immediately available for ES16. However, there is a discrepancy between the seed CSR specification and the privileged specification regarding the side effects of reads and writes. | |
| _2025-02-28_13：35：26_ | 2025-02-28 13：35：26 | | 从向量到矩阵：RISC-V 矩阵扩展的未来 - 知乎 --- From Vector to Matrix_ The Future of RISC-V Matrix Extensions - 知乎 | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: This text is about the development and future possibilities of Matrix Extensions in RISC-V, a open-source Instruction Set Architecture (ISA). The text discusses various matrix extension proposals, such as Integrated Matrix Extension from Spacemit and Attached Matrix Extension from Xuantie, Stream Computing, and SiFive (Zvma). The author compares the tradeoffs between Integrated and Attached Matrix Extensions, and the relationship between existing Vector Extensions and Matrix Extensions. The text also explores potential hardware implementations of RISC-V matrix acceleration.本文介绍了 RISC-V（一种开源指令集架构 （ISA））中矩阵扩展的开发和未来可能性。本文讨论了各种矩阵扩展提案，例如 Spacemit 的 Integrated Matrix Extension 和 Xuantie 的 Attached Matrix Extension、Stream Computing 和 SiFive （Zvma）。作者比较了 Integrated Matrix Extensions 和 Attached Matrix Extensions 之间的权衡，以及现有 Vector Extensions 和 Matrix Extensions 之间的关系。本文还探讨了 RISC-V 矩阵加速的潜在硬件实现。 | |
| _2025-02-28_13：40：48_ | 2025-02-28 13：40：48 | | 玄铁矩阵乘法扩展说明 – RISC-V International --- XuanTie Matrix Multiply Extension Instructions – RISC-V International | | 原文链接失效了?试试备份 | | TAGs:处理器 risc-v ISA | | Summary: The text discusses the XuanTie Matrix Multiply Extension (MME) for RISC-V processors, designed to meet the demands for AI computing power with independent matrix extensions. The benefits of independent matrix extensions include independent programming models, developer-friendly design, and simplified hardware implementation. The XuanTie MME includes matrix multiply-accumulate instructions, matrix load/store instructions, and other matrix computations to improve AI computing power. The extension supports various data types and sizes and is scalable, portable, and decoupled from vector extensions. The design has been open-sourced on GitHub for further development.本文讨论了用于 RISC-V 处理器的 XuanTie 矩阵乘法扩展 （MME），旨在通过独立的矩阵扩展满足对 AI 计算能力的需求。独立矩阵扩展的优势包括独立的编程模型、开发人员友好的设计和简化的硬件实现。炫铁 MME 包括矩阵乘法累加指令、矩阵加载/存储指令和其他矩阵计算，以提高 AI 计算能力。该扩展支持各种数据类型和大小，并且可扩展、可移植，并且与矢量扩展分离。该设计已在 GitHub 上开源，以供进一步开发。 | |