| _2025-02-28_14：00：26_ | 2025-02-28 14：00：26 | | tech-attached-matrix-extension@lists.riscv.org _RISC-V AME 扩展的 SiFive 提案 --- tech-attached-matrix-extension@lists.riscv.org _ | | TAGs:处理器 risc-v ISA Matrix | | Summary: This text is a discussion between team members regarding the Zvma Attached Matrix Extension (AME) proposal. They find the specification clear and elegant, offering significant matrix computation bandwidth while maintaining software-friendliness. However, they have some concerns about physical design friendliness, specifically the placement of matrix computation logic alongside RAM/flop states and the potential routing contention between the computation block and on-chip memory. They suggest making the data layout microarchitecture (uarch) defined instead of locked at the ISA level and allowing alternative punning schemes in future extensions for greater flexibility. They also recommend specifying that matrix data should be marked as "unspecified" following any matrix configuration change. The team is considering the uarch based on the proposal and looks forward to continued collaboration as Zvma progresses toward ratification.本文是团队成员之间关于 Zvma 附加矩阵扩展 （AME） 提案的讨论。他们发现规范清晰而优雅，在保持软件友好性的同时提供了大量的矩阵计算带宽。然而，他们对物理设计友好性有一些担忧，特别是矩阵计算逻辑与 RAM/flop 状态一起放置，以及计算块和片上存储器之间潜在的路由争用。他们建议在 ISA 级别定义而不是锁定数据布局微架构 （uarch），并在未来的扩展中允许使用其他双关模式以获得更大的灵活性。他们还建议指定在矩阵配置更改后应将矩阵数据标记为“未指定”。该团队正在根据该提案考虑 uarch，并期待在 Zvma 获得批准的过程中继续合作。 | |
| _2025-02-28_14：05：35_ | 2025-02-28 14：05：35 | | tech-attached-matrix-extension@lists.riscv.org _RISC-V AME 扩展的 SiFive 提案 --- tech-attached-matrix-extension@lists.riscv.org _ | | TAGs:处理器 risc-v ISA Matrix | | Summary: The text discusses a feedback exchange between team members regarding the Zvma Attached Matrix Extension (AME) proposal. The team, T1, has reviewed the proposal and finds it clear and elegant, offering significant matrix computation bandwidth while maintaining software-friendliness. They suggest some improvements, including making the data layout microarchitecture (uarch) defined instead of locked at the ISA level, addressing consistency challenges in multi-core scenarios, and specifying that matrix data should be marked as "unspecified" following any matrix configuration change. They also discuss concerns about physical design friendliness, specifically the placement of matrix computation logic alongside RAM/flop states and the potential routing contention between the computation block and on-chip memory. They emphasize the importance of addressing these issues to ensure high-performance computation and alignment across different uarch designs.本文讨论了团队成员之间关于 Zvma 附加矩阵扩展 （AME） 提案的反馈交流。T1 团队审查了该提案，发现它清晰而优雅，在保持软件友好性的同时提供了大量的矩阵计算带宽。他们提出了一些改进建议，包括在 ISA 级别定义而不是锁定数据布局微架构 （uarch），解决多核场景中的一致性挑战，以及指定在任何矩阵配置更改后应将矩阵数据标记为 “unspecified”。他们还讨论了对物理设计友好性的担忧，特别是矩阵计算逻辑与 RAM/flop 状态一起放置，以及计算块和片上存储器之间潜在的布线争用。他们强调了解决这些问题的重要性，以确保不同 uarch 设计之间的高性能计算和对齐。 | |
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| _2025_1_21_11：44：20_ | 2025_1_21 11：44：20 | | RISC-V Vector ISA-extensions | | TAGs:处理器 risc-v ISA | | saved date: Tue Jan 21 2025 11:44:20 GMT+0800 (中国标准时间) | |
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| _2025-02-26_11：29：14_ | 2025-02-26 11：29：14 | | tech-announce@lists.riscv.org _ Public review for Smctr_Ssctr ISA extensions | | TAGs:处理器 risc-v ISA | | Summary: The RISC-V Foundation has initiated a public review period for the proposed Control Transfer Records (Smctr/Ssctr) standard extensions to the RISC-V Instruction Set Architecture (ISA). The review period, which runs from July 23 to August 22, 2024, invites feedback via email or GitHub. The extensions, described in the PDF specification available at github.com, aim to correct and incorporate minor changes during the review process. The Privileged ISA Committee will recommend approval and ratification upon completion of the review. (by Mozilla Orbit AI) | |
| _2025-02-28_13：35：26_ | 2025-02-28 13：35：26 | | 从向量到矩阵：RISC-V 矩阵扩展的未来 - 知乎 --- From Vector to Matrix_ The Future of RISC-V Matrix Extensions - 知乎 | | TAGs:处理器 risc-v ISA | | Summary: This text is about the development and future possibilities of Matrix Extensions in RISC-V, a open-source Instruction Set Architecture (ISA). The text discusses various matrix extension proposals, such as Integrated Matrix Extension from Spacemit and Attached Matrix Extension from Xuantie, Stream Computing, and SiFive (Zvma). The author compares the tradeoffs between Integrated and Attached Matrix Extensions, and the relationship between existing Vector Extensions and Matrix Extensions. The text also explores potential hardware implementations of RISC-V matrix acceleration.本文介绍了 RISC-V（一种开源指令集架构 （ISA））中矩阵扩展的开发和未来可能性。本文讨论了各种矩阵扩展提案，例如 Spacemit 的 Integrated Matrix Extension 和 Xuantie 的 Attached Matrix Extension、Stream Computing 和 SiFive （Zvma）。作者比较了 Integrated Matrix Extensions 和 Attached Matrix Extensions 之间的权衡，以及现有 Vector Extensions 和 Matrix Extensions 之间的关系。本文还探讨了 RISC-V 矩阵加速的潜在硬件实现。 | |
| _2025-02-28_13：40：48_ | 2025-02-28 13：40：48 | | 玄铁矩阵乘法扩展说明 – RISC-V International --- XuanTie Matrix Multiply Extension Instructions – RISC-V International | | TAGs:处理器 risc-v ISA | | Summary: The text discusses the XuanTie Matrix Multiply Extension (MME) for RISC-V processors, designed to meet the demands for AI computing power with independent matrix extensions. The benefits of independent matrix extensions include independent programming models, developer-friendly design, and simplified hardware implementation. The XuanTie MME includes matrix multiply-accumulate instructions, matrix load/store instructions, and other matrix computations to improve AI computing power. The extension supports various data types and sizes and is scalable, portable, and decoupled from vector extensions. The design has been open-sourced on GitHub for further development.本文讨论了用于 RISC-V 处理器的 XuanTie 矩阵乘法扩展 （MME），旨在通过独立的矩阵扩展满足对 AI 计算能力的需求。独立矩阵扩展的优势包括独立的编程模型、开发人员友好的设计和简化的硬件实现。炫铁 MME 包括矩阵乘法累加指令、矩阵加载/存储指令和其他矩阵计算，以提高 AI 计算能力。该扩展支持各种数据类型和大小，并且可扩展、可移植，并且与矢量扩展分离。该设计已在 GitHub 上开源，以供进一步开发。 | |