|
|
| _2025-05-15_15：08：26_ | 2025-05-15 15：08：26 | | BlueField Supported Interfaces - NVIDIA Docs | | 原文链接失效了?试试备份 | | TAGs:DPU DPU 介绍 | | Summary: NVIDIA BlueField-3 is a System-on-Chip (SoC) that integrates a 64-bit Armv8.2+ A78 Hercules cores array, an NVIDIA ConnectX-7 network adapter front-end, and a PCI Express switch. It features an Armv multicore processor array for advanced application development and software ecosystem support. The ConnectX-7 network offload controller delivers high performance for networking and storage applications, with RDMA and RoCE technology, an embedded virtual switch with ACLs, and transport offloads for NVMe over Fabrics, VXLAN, and MPLS overlay protocols.NVIDIA BlueField-3 是一款系统级芯片 （SoC），集成了 64 位 Armv8.2+ A78 Hercules 内核阵列、NVIDIA ConnectX-7 网络适配器前端和 PCI Express 交换机。它具有 Armv 多核处理器阵列，用于高级应用程序开发和软件生态系统支持。ConnectX-7 网络卸载控制器采用 RDMA 和 RoCE 技术、带 ACL 的嵌入式虚拟交换机，以及 NVMe over Fabrics、VXLAN 和 MPLS 叠加协议的传输卸载，为网络和存储应用程序提供高性能。 | |
| _2025-05-15_15：08：26_ | 2025-05-15 15：08：26 | | BlueField Supported Interfaces - NVIDIA Docs | | 原文链接失效了?试试备份 | | TAGs:DPU DPU 介绍 | | Summary: NVIDIA BlueField-3 is a System-on-Chip (SoC) that integrates a 64-bit Armv8.2+ A78 Hercules cores array, an NVIDIA ConnectX-7 network adapter front-end, and a PCI Express switch. It features an Armv multicore processor array for advanced application development and software ecosystem support. The ConnectX-7 network offload controller delivers high performance for networking and storage applications, with RDMA and RoCE technology, an embedded virtual switch with ACLs, and transport offloads for NVMe over Fabrics, VXLAN, and MPLS overlay protocols.NVIDIA BlueField-3 是一款系统级芯片 （SoC），集成了 64 位 Armv8.2+ A78 Hercules 内核阵列、NVIDIA ConnectX-7 网络适配器前端和 PCI Express 交换机。它具有 Armv 多核处理器阵列，用于高级应用程序开发和软件生态系统支持。ConnectX-7 网络卸载控制器采用 RDMA 和 RoCE 技术、带 ACL 的嵌入式虚拟交换机，以及 NVMe over Fabrics、VXLAN 和 MPLS 叠加协议的传输卸载，为网络和存储应用程序提供高性能。 | |
|
|
|
|
|
|
| _2025-05-14_12：01：56_ | 2025-05-14 12：01：56 | | 《考察报告》连载九｜从SmartNIC到DPU、IPU - 知乎 | | 原文链接失效了?试试备份 | | TAGs:DPU DPU 介绍 | | Summary: This text is about the evolution of data processing technology, from SmartNICs to DPUs and IPUs, focusing on distributed computing and the need for high-speed networking to connect distributed computing power. The text discusses how SmartNICs, which offload tasks from CPUs, have been replaced by DPUs and IPUs, which offer more control and acceleration at the processing level. The text mentions Intel's BlueField-3 DPU and Marvell's OCTEON 10 DPU as examples of these technologies. DPUs and IPUs differ from SmartNICs in that they have control planes and can be self-managed, allowing for more efficient and secure large-scale computing applications. The text also mentions Facebook's report on the benefits of IPUs in microservices architecture and the advantages of using IPUs instead of CPUs for infrastructure processing.本文介绍了数据处理技术的演变，从 SmartNIC 到 DPU 和 IPU，重点介绍分布式计算和连接分布式计算能力的高速网络需求。本文讨论了从 CPU 卸载任务的 SmartNIC 如何被 DPU 和 IPU 所取代，后者在处理级别提供更多控制和加速。文中提到了 Intel 的 BlueField-3 DPU 和 Marvell 的 OCTEON 10 DPU 作为这些技术的示例。DPU 和 IPU 与 SmartNIC 的不同之处在于，它们具有控制平面，并且可以自我管理，从而实现更高效、更安全的大规模计算应用程序。该文本还提到了 Facebook 关于 IPU 在微服务架构中的优势以及使用 IPU 而不是 CPU 进行基础设施处理的优势的报告。 | |
| _2025-05-14_12：01：56_ | 2025-05-14 12：01：56 | | 《考察报告》连载九｜从SmartNIC到DPU、IPU - 知乎 | | 原文链接失效了?试试备份 | | TAGs:DPU DPU 介绍 | | Summary: This text is about the evolution of data processing technology, from SmartNICs to DPUs and IPUs, focusing on distributed computing and the need for high-speed networking to connect distributed computing power. The text discusses how SmartNICs, which offload tasks from CPUs, have been replaced by DPUs and IPUs, which offer more control and acceleration at the processing level. The text mentions Intel's BlueField-3 DPU and Marvell's OCTEON 10 DPU as examples of these technologies. DPUs and IPUs differ from SmartNICs in that they have control planes and can be self-managed, allowing for more efficient and secure large-scale computing applications. The text also mentions Facebook's report on the benefits of IPUs in microservices architecture and the advantages of using IPUs instead of CPUs for infrastructure processing.本文介绍了数据处理技术的演变，从 SmartNIC 到 DPU 和 IPU，重点介绍分布式计算和连接分布式计算能力的高速网络需求。本文讨论了从 CPU 卸载任务的 SmartNIC 如何被 DPU 和 IPU 所取代，后者在处理级别提供更多控制和加速。文中提到了 Intel 的 BlueField-3 DPU 和 Marvell 的 OCTEON 10 DPU 作为这些技术的示例。DPU 和 IPU 与 SmartNIC 的不同之处在于，它们具有控制平面，并且可以自我管理，从而实现更高效、更安全的大规模计算应用程序。该文本还提到了 Facebook 关于 IPU 在微服务架构中的优势以及使用 IPU 而不是 CPU 进行基础设施处理的优势的报告。 | |
|
|
|
|
| _2025-05-14_11：57：47_ | 2025-05-14 11：57：47 | | 浅析SmartNIC：博通vs英特尔vs英伟达vs赛灵思 | | 原文链接失效了?试试备份 | | TAGs:DPU DPU 介绍 | | Summary: This article discusses the difference between traditional Network Interface Cards (NICs) and SmartNICs. While NICs are built around ASICs designed as ethernet controllers, SmartNICs are defined as network cards that allow software to be loaded onto the NIC after purchase to add new features or support other functions. The main difference between a regular NIC and a SmartNIC is that the latter offloads processing from the host CPU and is designed around FPGA platforms. SmartNICs require additional computational power and onboard memory, which regular NICs lack. The article compares the SmartNIC offerings of six companies: Broadcom (Brocade), Intel, Nvidia (Mellanox), Xilinx (Xilinx), Netronome, and Pensando. Broadcom's Stingray SmartNIC uses a single chip method, while Intel's N3000 SmartNIC uses multiple chips. Xilinx's Alveo U25 uses a Zynq SoC, which includes an FPGA and an Arm CPU. Pensando's DSC-25 uses a Capri processor with parallel P4 processing units. The article also discusses the potential benefits of SmartNICs, such as offloading network processing tasks from the host CPU and extending computing power to the network edge.本文讨论了传统网络接口卡 （NIC） 和 SmartNIC 之间的区别。NIC 是围绕设计为以太网控制器的 ASIC 构建的，而 SmartNIC 则被定义为允许在购买后将软件加载到 NIC 上以添加新功能或支持其他功能的网卡。常规 NIC 和 SmartNIC 之间的主要区别在于，后者从主机 CPU 卸载处理，并且是围绕 FPGA 平台设计的。SmartNIC 需要额外的计算能力和板载内存，而普通 NIC 则缺乏这些。本文比较了六家公司的 SmartNIC 产品：Broadcom （Brocade）、Intel、Nvidia （Mellanox）、Xilinx （Xilinx）、Netronome 和 Pensando。Broadcom 的 Stingray SmartNIC 使用单芯片方法，而 Intel 的 N3000 SmartNIC 使用多芯片。Xilinx 的 Alveo U25 使用 Zynq SoC，其中包括一个 FPGA 和一个 Arm CPU。Pensand 的 DSC-25 使用带有并行 P4 处理单元的 Capri 处理器。本文还讨论了 SmartNIC 的潜在优势，例如从主机 CPU 卸载网络处理任务，并将计算能力扩展到网络边缘。 | |
| _2025-05-14_11：57：47_ | 2025-05-14 11：57：47 | | 浅析SmartNIC：博通vs英特尔vs英伟达vs赛灵思 | | 原文链接失效了?试试备份 | | TAGs:DPU DPU 介绍 | | Summary: This article discusses the difference between traditional Network Interface Cards (NICs) and SmartNICs. While NICs are built around ASICs designed as ethernet controllers, SmartNICs are defined as network cards that allow software to be loaded onto the NIC after purchase to add new features or support other functions. The main difference between a regular NIC and a SmartNIC is that the latter offloads processing from the host CPU and is designed around FPGA platforms. SmartNICs require additional computational power and onboard memory, which regular NICs lack. The article compares the SmartNIC offerings of six companies: Broadcom (Brocade), Intel, Nvidia (Mellanox), Xilinx (Xilinx), Netronome, and Pensando. Broadcom's Stingray SmartNIC uses a single chip method, while Intel's N3000 SmartNIC uses multiple chips. Xilinx's Alveo U25 uses a Zynq SoC, which includes an FPGA and an Arm CPU. Pensando's DSC-25 uses a Capri processor with parallel P4 processing units. The article also discusses the potential benefits of SmartNICs, such as offloading network processing tasks from the host CPU and extending computing power to the network edge.本文讨论了传统网络接口卡 （NIC） 和 SmartNIC 之间的区别。NIC 是围绕设计为以太网控制器的 ASIC 构建的，而 SmartNIC 则被定义为允许在购买后将软件加载到 NIC 上以添加新功能或支持其他功能的网卡。常规 NIC 和 SmartNIC 之间的主要区别在于，后者从主机 CPU 卸载处理，并且是围绕 FPGA 平台设计的。SmartNIC 需要额外的计算能力和板载内存，而普通 NIC 则缺乏这些。本文比较了六家公司的 SmartNIC 产品：Broadcom （Brocade）、Intel、Nvidia （Mellanox）、Xilinx （Xilinx）、Netronome 和 Pensando。Broadcom 的 Stingray SmartNIC 使用单芯片方法，而 Intel 的 N3000 SmartNIC 使用多芯片。Xilinx 的 Alveo U25 使用 Zynq SoC，其中包括一个 FPGA 和一个 Arm CPU。Pensand 的 DSC-25 使用带有并行 P4 处理单元的 Capri 处理器。本文还讨论了 SmartNIC 的潜在优势，例如从主机 CPU 卸载网络处理任务，并将计算能力扩展到网络边缘。 | |
|
|
|
|
|
|
| _2025-03-24_19：33：49_ | 2025-03-24 19：33：49 | | 使用 CXL 提升存储堆栈或服务工作流的软硬件处理流水线-INTEL-腾讯云开发者社区-腾讯云 | | 原文链接失效了?试试备份 | | TAGs:DPU | | Summary: This text is about the use of Intel's DPU (Data Processing Unit) with CXL (Compute Express Link) to enhance storage stack performance and service workflows. The article discusses the challenges of CPU+DPU cooperative processing, the benefits of using a single shared memory domain between CPU and DPU, and the advantages of using SPDK software stack for CPU+DPU cooperative processing with CXL. The article also mentions the importance of building high-performance storage solutions and the challenges of current accelerator offloading technology in meeting the growing demand for high-performance secure storage solutions.本文是关于将英特尔的 DPU（数据处理单元）与 CXL （Compute Express Link） 结合使用来增强存储堆栈性能和服务工作流程的。本文讨论了 CPU+DPU 协同处理的挑战、在 CPU 和 DPU 之间使用单个共享内存域的好处，以及使用 SPDK 软件堆栈进行 CPU+DPU 与 CXL 协同处理的优势。文章还提到了构建高性能存储解决方案的重要性，以及当前加速器卸载技术在满足对高性能安全存储解决方案日益增长的需求方面面临的挑战。 | |
|
|
|
|
|
| _2024_8_19_15_50_27_ | 2024_8_19 15_50_27 | | P4 学习笔记 - 知乎 | | 原文链接失效了?试试备份 | | TAGs:DPU P4 | | saved date: Mon Aug 19 2024 15:50:27 GMT+0800 (中国标准时间) | |
|
|
|
| _2025-04-23_21：06：00_ | 2025-04-23 21：06：00 | | DPUaudit_ DPU-assisted Pull-based Architecture for Near-Zero Cost System Auditing _ IEEE Conference Publication _ IEEE Xplore | | 原文链接失效了?试试备份 | | TAGs:DPU 应用 | | Summary: This text is about a research paper titled "DPUaudit: DPU-assisted Pull-based Architecture for Near-Zero Cost System Auditing," published in the 2025 IEEE International Symposium on High Performance Computer Architecture. The paper proposes a new hardware-based auditing framework called DPUaudit, which utilizes DPU to pull system events from the monitored host instead of using a log sender. This pull-based architecture eliminates the need for heavy software protection mechanisms, resulting in near-zero runtime overhead and efficient system auditing. The experimental results show that DPUaudit only slows down applications on the monitored host by an average of 2.1%, which is significantly less than existing approaches.本文是关于一篇题为“DPUaudit：用于近零成本系统审计的 DPU 辅助拉式架构”的研究论文，该论文发表在 2025 年 IEEE 高性能计算机体系结构国际研讨会上。该白皮书提出了一种称为 DPUaudit 的基于硬件的新审计框架，该框架利用 DPU 从受监控主机中提取系统事件，而不是使用日志发件人。这种基于拉取的架构消除了对繁重的软件保护机制的需求，从而实现了近乎零的运行时开销和高效的系统审计。实验结果表明，DPUaudit 仅使受监控主机上的应用程序平均减慢 2.1%，这明显低于现有方法。 | |
|
|