_2025-03-03_15：34：56_ 2025-03-03 15：34：56 RISCV Landscape TAGs:处理器 risc-v RISC-V Software Ecosystem Summary:

_2025-03-03_14：06：53_ 2025-03-03 14：06：53 HAPS-100_ High-Performance Scalable Prototyping System _ Synopsys TAGs:半导体 EDA Summary: Synopsys is a leading provider of electronic design automation solutions and services, offering a range of products for design, verification, and manufacturing of semiconductors. Their offerings include silicon IP, verification IP, and design tools, as well as emulation and prototyping systems like HAPS-200 and ZeBu-200 for faster prototyping and software development. HAPS-100 is their highest performance and most scalable pre-silicon prototyping system, designed for software development and validation with the fastest performance and highest debug productivity.Synopsys 是电子设计自动化解决方案和服务提供商，提供一系列用于半导体设计、验证和制造的产品。他们的产品包括硅 IP、验证 IP 和设计工具，以及 HAPS-200 和 ZeBu-200 等仿真和原型系统，用于加快原型设计和软件开发。HAPS-100 是其最高性能和最具可扩展性的硅前原型系统，专为软件开发和验证而设计，具有最快的性能和最高的调试效率。

_2025-03-02_17：17：38_ 2025-03-02 17：17：38 首页 _ MiGPT GUI TAGs:AI应用 Summary: This page introduces MiGPT, a GUI for securely and quickly integrating your XiaoAI box with artificial intelligence. It also provides additional GitHub links for further use and text-to-speech translation.本页介绍了 MiGPT，这是一个用于安全快速地将你的小爱盒子与人工智能集成的 GUI。它还提供了其他 GitHub 链接，以供进一步使用和文本到语音转换。

_2025-03-02_13：58：48_ 2025-03-02 13：58：48 SR-IOV Configuration Guide—Intel® Ethernet CNA X710 & XL710 on SuSE Linux_ Enterprise Server 12__ Technical Brief TAGs:虚拟化&容器 IO SR-IOV Summary: This page is about the configuration guide for using Intel Ethernet CNA X710 and XL710 series adapters on SuSE Linux Enterprise Server 12 for SR-IOV. The page introduces the Intel Ethernet Controllers X710 and XL710, and the Intel Ethernet Converged Network Adapter X710 Series and Intel Ethernet Server Adapter XL710. The page explains that these ethernet products offer world-class 40 GbE support and compatibility with popular Linux distributions for I/O virtualization. The usage instructions and company information are also provided.本页介绍在 SuSE Linux Enterprise Server 12 for SR-IOV 上使用 Intel 以太网 CNA X710 和 XL710 系列适配器的配置指南。本页介绍了 Intel 以太网控制器 X710 和 XL710，以及 Intel 以太网融合网络适配器 X710 系列和 Intel 以太网服务器适配器 XL710。该页面介绍了这些以太网产品提供世界一流的 40 GbE 支持，并与流行的 Linux 发行版兼容，以实现 I/O 虚拟化。此外，还提供了使用说明和公司信息。

_2025-03-02_11：24：49_ 2025-03-02 11：24：49 riscv-non-isa_riscv-server-platform_ The RISC-V Server Platform specification defines a standardized set of hardware and sofwa TAGs:处理器 risc-v server Summary: The RISC-V Server Platform is a specification that outlines standardized hardware and software capabilities for portable system software, such as operating systems and hypervisors, in RISC-V servers. The document includes information about the specification, its history, and dependencies. Users can clone the project, build the PDF using the Makefile, and view the document's topics, which include platform, server, os, standards, interoperability, UEFi, hypervisors, ACPI, risc-v, and BRS-I. The project is licensed under a Creative Commons Attribution 4.0 International License and has 11 stars, 5 forks, and 8 watchers.RISC-V 服务器平台是一项规范，概述了 RISC-V 服务器中便携式系统软件（如作系统和虚拟机管理程序）的标准化硬件和软件功能。该文档包含有关规范、其历史记录和依赖项的信息。用户可以克隆项目，使用 Makefile 构建 PDF，并查看文档的主题，包括平台、服务器、作系统、标准、互作性、UEFi、虚拟机管理程序、ACPI、risc-v 和 BRS-I。该项目根据 Creative Commons Attribution 4.0 International License 获得许可，并拥有 11 颗星、5 个分叉和 8 个观察者。

_2025-03-02_10：46：18_ 2025-03-02 10：46：18 首页 _ MiGPT GUI TAGs:AI应用 Summary: This page introduces MiGPT, a GUI for securely and quickly integrating your Xiaoice box with artificial intelligence. It also provides additional GitHub links for further use and text-to-speech translation.本页介绍了 MiGPT，这是一个用于安全快速地将小冰盒与人工智能集成的 GUI。它还提供了其他 GitHub 链接，以供进一步使用和文本到语音转换。

_2025-02-28_18：20：02_ 2025-02-28 18：20：02 deepseek-ai_DeepGEMM： DeepGEMM： 干净高效的 FP8 GEMM 内核，具有细粒度扩展 --- deepseek-ai_DeepGEMM_ DeepGEMM_ clean and efficient FP8 GEMM ker TAGs:大模型 Summary: DeepGEMM is a library designed for clean and efficient FP8 General Matrix Multiplications (GEMMs) with fine-grained scaling, using Hopper architecture GPUs and CUDA 12.3 or above. It supports both normal and Mix-of-Experts (MoE) grouped GEMMs, with various optimizations such as warp-specialization, TMA features, and a fully JIT design. The library also provides utility functions and environment variables.DeepGEMM 是一个库，旨在使用 Hopper 架构 GPU 和 CUDA 12.3 或更高版本，实现干净高效的 FP8 通用矩阵乘法 （GEMM），进行精细缩放。它支持普通和混合专家 （MoE） 分组 GEMM，具有各种优化，例如 warp 专业化、TMA 功能和完全 JIT 设计。该库还提供实用程序函数和环境变量。

_2025-02-28_14：05：35_ 2025-02-28 14：05：35 tech-attached-matrix-extension@lists.riscv.org _RISC-V AME 扩展的 SiFive 提案 --- tech-attached-matrix-extension@lists.riscv.org _ TAGs:处理器 risc-v ISA Matrix Summary: The text discusses a feedback exchange between team members regarding the Zvma Attached Matrix Extension (AME) proposal. The team, T1, has reviewed the proposal and finds it clear and elegant, offering significant matrix computation bandwidth while maintaining software-friendliness. They suggest some improvements, including making the data layout microarchitecture (uarch) defined instead of locked at the ISA level, addressing consistency challenges in multi-core scenarios, and specifying that matrix data should be marked as "unspecified" following any matrix configuration change. They also discuss concerns about physical design friendliness, specifically the placement of matrix computation logic alongside RAM/flop states and the potential routing contention between the computation block and on-chip memory. They emphasize the importance of addressing these issues to ensure high-performance computation and alignment across different uarch designs.本文讨论了团队成员之间关于 Zvma 附加矩阵扩展 （AME） 提案的反馈交流。T1 团队审查了该提案，发现它清晰而优雅，在保持软件友好性的同时提供了大量的矩阵计算带宽。他们提出了一些改进建议，包括在 ISA 级别定义而不是锁定数据布局微架构 （uarch），解决多核场景中的一致性挑战，以及指定在任何矩阵配置更改后应将矩阵数据标记为 “unspecified”。他们还讨论了对物理设计友好性的担忧，特别是矩阵计算逻辑与 RAM/flop 状态一起放置，以及计算块和片上存储器之间潜在的布线争用。他们强调了解决这些问题的重要性，以确保不同 uarch 设计之间的高性能计算和对齐。

_2025-02-28_14：00：26_ 2025-02-28 14：00：26 tech-attached-matrix-extension@lists.riscv.org _RISC-V AME 扩展的 SiFive 提案 --- tech-attached-matrix-extension@lists.riscv.org _ TAGs:处理器 risc-v ISA Matrix Summary: This text is a discussion between team members regarding the Zvma Attached Matrix Extension (AME) proposal. They find the specification clear and elegant, offering significant matrix computation bandwidth while maintaining software-friendliness. However, they have some concerns about physical design friendliness, specifically the placement of matrix computation logic alongside RAM/flop states and the potential routing contention between the computation block and on-chip memory. They suggest making the data layout microarchitecture (uarch) defined instead of locked at the ISA level and allowing alternative punning schemes in future extensions for greater flexibility. They also recommend specifying that matrix data should be marked as "unspecified" following any matrix configuration change. The team is considering the uarch based on the proposal and looks forward to continued collaboration as Zvma progresses toward ratification.本文是团队成员之间关于 Zvma 附加矩阵扩展 （AME） 提案的讨论。他们发现规范清晰而优雅，在保持软件友好性的同时提供了大量的矩阵计算带宽。然而，他们对物理设计友好性有一些担忧，特别是矩阵计算逻辑与 RAM/flop 状态一起放置，以及计算块和片上存储器之间潜在的路由争用。他们建议在 ISA 级别定义而不是锁定数据布局微架构 （uarch），并在未来的扩展中允许使用其他双关模式以获得更大的灵活性。他们还建议指定在矩阵配置更改后应将矩阵数据标记为“未指定”。该团队正在根据该提案考虑 uarch，并期待在 Zvma 获得批准的过程中继续合作。

_2025-02-28_13：40：48_ 2025-02-28 13：40：48 玄铁矩阵乘法扩展说明 – RISC-V International --- XuanTie Matrix Multiply Extension Instructions – RISC-V International TAGs:处理器 risc-v ISA Summary: The text discusses the XuanTie Matrix Multiply Extension (MME) for RISC-V processors, designed to meet the demands for AI computing power with independent matrix extensions. The benefits of independent matrix extensions include independent programming models, developer-friendly design, and simplified hardware implementation. The XuanTie MME includes matrix multiply-accumulate instructions, matrix load/store instructions, and other matrix computations to improve AI computing power. The extension supports various data types and sizes and is scalable, portable, and decoupled from vector extensions. The design has been open-sourced on GitHub for further development.本文讨论了用于 RISC-V 处理器的 XuanTie 矩阵乘法扩展 （MME），旨在通过独立的矩阵扩展满足对 AI 计算能力的需求。独立矩阵扩展的优势包括独立的编程模型、开发人员友好的设计和简化的硬件实现。炫铁 MME 包括矩阵乘法累加指令、矩阵加载/存储指令和其他矩阵计算，以提高 AI 计算能力。该扩展支持各种数据类型和大小，并且可扩展、可移植，并且与矢量扩展分离。该设计已在 GitHub 上开源，以供进一步开发。

_2025-02-28_13：35：26_ 2025-02-28 13：35：26 从向量到矩阵：RISC-V 矩阵扩展的未来 - 知乎 --- From Vector to Matrix_ The Future of RISC-V Matrix Extensions - 知乎 TAGs:处理器 risc-v ISA Summary: This text is about the development and future possibilities of Matrix Extensions in RISC-V, a open-source Instruction Set Architecture (ISA). The text discusses various matrix extension proposals, such as Integrated Matrix Extension from Spacemit and Attached Matrix Extension from Xuantie, Stream Computing, and SiFive (Zvma). The author compares the tradeoffs between Integrated and Attached Matrix Extensions, and the relationship between existing Vector Extensions and Matrix Extensions. The text also explores potential hardware implementations of RISC-V matrix acceleration.本文介绍了 RISC-V（一种开源指令集架构 （ISA））中矩阵扩展的开发和未来可能性。本文讨论了各种矩阵扩展提案，例如 Spacemit 的 Integrated Matrix Extension 和 Xuantie 的 Attached Matrix Extension、Stream Computing 和 SiFive （Zvma）。作者比较了 Integrated Matrix Extensions 和 Attached Matrix Extensions 之间的权衡，以及现有 Vector Extensions 和 Matrix Extensions 之间的关系。本文还探讨了 RISC-V 矩阵加速的潜在硬件实现。

_2025-02-28_10：11：19_ 2025-02-28 10：11：19 GiantVM_ a type-II hypervisor implementing many-to-one virtualization _ Proceedings of the 16th ACM SIGPLAN_SIGOPS Internation TAGs:虚拟化&容器 多虚一 Summary: This paper introduces GiantVM, an open-source distributed hypervisor that provides many-to-one virtualization to aggregate resources from multiple physical machines and offers a uniform hardware abstraction for guest OSes. GiantVM combines the benefits of scale-up and scale-out solutions, enabling unmodified applications to run with a huge amount of physical resources. It also leverages distributed shared memory to achieve aggregation of memory and proposes techniques to deal with the challenges of CPU and I/O virtualization in distributed environments. The authors have implemented GiantVM based on the state-of-the-art type-II hypervisor QEMU-KVM and it can currently host conventional OSes such as Linux. Evaluations show that GiantVM outperforms Spark by up to 3.4X with two text-processing programs.本文介绍了 GiantVM，这是一种开源分布式管理程序，它提供多对一虚拟化来聚合来自多个物理机的资源，并为来宾作系统提供统一的硬件抽象。GiantVM 结合了纵向扩展和横向扩展解决方案的优势，使未经修改的应用程序能够使用大量物理资源运行。它还利用分布式共享内存来实现内存聚合，并提出了应对分布式环境中 CPU 和 I/O 虚拟化挑战的技术。作者基于最先进的 II 类管理程序 QEMU-KVM 实现了 GiantVM，它目前可以托管 Linux 等传统作系统。评估表明，GiantVM 使用两个文本处理程序的性能比 Spark 高出 3.4 倍。

_2025-02-28_09：59：02_ 2025-02-28 09：59：02 GiantVM TAGs:虚拟化&容器 产品 多虚一 Summary: GiantVM is a distributed hypervisor that utilizes resources from multiple physical machines, offering a uniform hardware abstraction to the guest OS through techniques like IPI, interrupt, and I/O forwarding. It's based on QEMU-KVM and distributed shared memory (DSM) technology. The input includes instructions on how to install and run GiantVM on a single machine using Ubuntu 16.04.7 and Linux-DSM. The paper "GiantVM: A Type-II Hypervisor Implementing Many-to-one Virtualization" was published in the Proceedings of the 16th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments in 2020. The authors include Zhengwei Qi, Haibing Guan, and others from Shanghai Jiao Tong University.GiantVM 是一个分布式管理程序，它利用来自多个物理机的资源，通过 IPI、中断和 I/O 转发等技术为来宾作系统提供统一的硬件抽象。它基于 QEMU-KVM 和分布式共享内存 （DSM） 技术。输入包括有关如何使用 Ubuntu 16.04.7 和 Linux-DSM 在单台计算机上安装和运行 GiantVM 的说明。论文《GiantVM：实现多对一虚拟化的 Type-II Hypervisor》发表在 2020 年第 16 届 ACM SIGPLAN/SIGOPS 虚拟执行环境国际会议的论文集上。作者包括来自上海交通大学的 Zhengwei Qi、Haibing Guan 等人。

_2025-02-27_17：36：45_ 2025-02-27 17：36：45 清华大学出版社-图书详情-《深入浅出系统虚拟化：原理与实践》 TAGs:虚拟化&容器 书 Summary: This book is a professional text on system virtualization. It covers the principles and practices of system virtualization, including its history, trends, and main functions and classifications. The book also introduces various types of virtualization systems, such as openEuler, and explains how they implement CPU and interrupt virtualization using QEMU/KVM and GiantVM. The book is written by Qi Zhengwei, a professor at Shanghai Jiao Tong University, and is aimed at readers with a basic understanding of hardware architecture and operating systems. It is a comprehensive resource for understanding system virtualization technology.

_2025-02-27_17：07：00_ 2025-02-27 17：07：00 GiantVM_ GiantVM，又称巨型虚拟机，是一个基于 QEMU-KVM 的_多虚一_分布式Type II型hypervisor TAGs:虚拟化&容器 产品 Summary: GiantVM is a distributed Type II hypervisor developed by the Shanghai Jiao Tong University Can-Extend Computing and System Experiment Laboratory Can-Trust Cloud Computing Team. It manages resources from multiple physical machines and provides a unified hardware abstraction for customer operating systems. GiantVM uses RDMA technology for hardware abstraction at the virtualization level, and provides distributed QEMU for cross-node virtual machine abstraction, KVM for lower-level physical machine management, and low-latency distributed shared memory DSM. GiantVM has two main code repositories: Linux-DSM and QEMU, each containing corresponding modifications to KVM and QEMU. To join, send an application email to xiangyuxin@sjtu.edu.cn. Gitee is a Chinese open-source code hosting platform with features like GitHub, including importing GitHub repositories and Git commands.GiantVM 是由上海交通大学 Can-Extend 计算与系统实验实验室 Can-Trust 云计算团队开发的分布式 Type II 管理程序。它管理来自多个物理机的资源，并为客户作系统提供统一的硬件抽象。GiantVM 在虚拟化级别使用 RDMA 技术进行硬件抽象，并提供分布式 QEMU 用于跨节点虚拟机抽象，KVM 用于低级物理机管理，以及低延迟分布式共享内存 DSM。GiantVM 有两个主要的代码仓库：Linux-DSM 和 QEMU，每个代码仓库都包含对 KVM 和 QEMU 的相应修改。要加入，请向 xiangyuxin@sjtu.edu.cn 发送申请电子邮件。Gitee 是一个中国开源代码托管平台，具有 GitHub 等功能，包括导入 GitHub 仓库和 Git 命令。

_2025-02-27_11：58：26_ 2025-02-27 11：58：26 DeepSeek开源周总结和感悟【更新至第三天】 - 知乎 TAGs:处理器 异构计算 软硬协同 大模型 Summary: This text is a summary of a blog post about DeepSeek, an open-source project that optimizes AI performance on specific hardware. The author expresses their feelings about the challenges of completing such work in foreign AI companies due to hardware restrictions. They highlight three projects, FlashMLA, DeepEP, and DeepGEMM, and their contributions to improving AI performance on limited hardware. The author emphasizes the importance of understanding both AI models and hardware for optimal performance and the potential impact of DeepSeek on the industry.本文是关于 DeepSeek 的博客文章的摘要，DeepSeek 是一个开源项目，可优化特定硬件上的 AI 性能。作者表达了他们对由于硬件限制而在国外 AI 公司完成此类工作所面临的挑战的感受。他们重点介绍了 FlashMLA、DeepEP 和 DeepGEMM 三个项目，以及它们对在有限硬件上提高 AI 性能的贡献。作者强调了了解 AI 模型和硬件以实现最佳性能的重要性，以及 DeepSeek 对行业的潜在影响。

_2025-02-27_11：32：05_ 2025-02-27 11：32：05 芯华章X-EPIC _ 从芯定义智慧未来 TAGs:半导体 EDA Summary: X-Epic Tech is a Chinese EDA (Electronic Design Automation) company that focuses on creating agile verification solutions from chips to systems. They have developed over 200 patent applications and released several commercial-level verification products based on platformization, intelligence, and cloudization. Their offerings include a comprehensive digital verification full process EDA tool and seven product series covering hardware emulation systems, FPGA prototype verification systems, intelligent scene verification, static and formal verification, logic emulation, system debugging, and verification clouds. They have collaborated with various partners to enhance their RISC-V chip verification and testing solutions, and have received certifications from international standards such as ISO 26262. They have also received strategic investments from major funds and companies. Their research institute was established in 2017 to develop the next generation of EDA 2.0 technology. They have also opened an open-source EDA technology community, EDAGit.com, to lower the threshold for using formal verification tools. They have received numerous awards for their high-performance FPGA prototype verification system and high-performance hardware emulation system. They can be contacted for communications, business sales, recruitment, and foreign research collaborations.X-Epic Tech 是一家中国的 EDA（电子设计自动化）公司，专注于创建从芯片到系统的敏捷验证解决方案。他们开发了 200 多项专利申请，并发布了多款基于平台化、智能化和云化的商业级验证产品。他们的产品包括全面的数字验证全流程 EDA 工具和七大产品系列，涵盖硬件仿真系统、FPGA 原型验证系统、智能场景验证、静态和形式化验证、逻辑仿真、系统调试和验证云。他们与各种合作伙伴合作，以增强其 RISC-V 芯片验证和测试解决方案，并已获得 ISO 26262 等国际标准的认证。他们还获得了来自主要基金和公司的战略投资。他们的研究所成立于 2017 年，旨在开发下一代 EDA 2.0 技术。他们还开设了一个开源的 EDA 技术社区 EDAGit.com，以降低使用形式化验证工具的门槛。他们凭借其高性能 FPGA 原型验证系统和高性能硬件仿真系统获得了无数奖项。可以联系他们进行沟通、业务销售、招聘和外国研究合作。

_2025_2_27_11：20：22_ 2025_2_27 11：20：22 芯华章X-EPIC ： 从芯定义智慧未来 TAGs: saved date: Thu Feb 27 2025 11:20:22 GMT+0800 (中国标准时间)

_2025_2_27_11：16：08_ 2025_2_27 11：16：08 芯华章X-EPIC ： 从芯定义智慧未来 TAGs:半导体 EDA saved date: Thu Feb 27 2025 11:16:08 GMT+0800 (中国标准时间)

_2025-02-26_16：35：36_ 2025-02-26 16：35：36 RISC-V Non-ISA Specifications TAGs:处理器 risc-v Summary: This text describes the RISC-V Non-ISA Specifications repository on GitHub, which contains non-instruction set architecture specifications for RISC-V. These specifications include documentation, architecture tests, and specifications for various interfaces and tools. The repository includes several sub-repositories, each focusing on different aspects of the RISC-V ecosystem. The text also mentions that the repository does not modify the RISC-V Instruction Set Architecture and provides a list of popular repositories.